I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread.
Is there such a demo out, mentioned in the thread?
I read in several groups that it is a problem to get this DDR Ram running ?
I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread.
Is there such a demo out, mentioned in the thread?
I read in several groups that it is a problem to get this DDR Ram running ?
I'm not sure what you're refering to, but David Ashley ported the OpenCore DDR SDRAM controller to the Spartan-3E500 start kit and posted it here. I only had to adjust the .ucf file a bit to get it on the Spartan-3E1600 Starter kit.
Tommy
I should probably add: More information on MIG can be found on the Memory Corner on xilinx.com:
xilinx.com:http://www.xilinx.com/products/design_resources/mem_corner/
Looks like my first message was not posted correctly: The Xilinx Memory Interface Generator (MIG) generates ready-to-use HDL for the Spartan-3E Startker Kit.
Cheers, Jaco
Aha! So two chances to get a controller. Will try this ! Thanks to both of you!
I downloaded the reference design but did only find verilog files which i cannot use. the re also ssems to be an ngc file missing, which is nowhere in the zip archiv.
Isn't there a working project for ISE 8/9 which directly compiles and produces some test ?
-- Concerning the other design: I found the .../dash/ocddr design. This is one file, which I do not know how to handle. I had been able to
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