Spartan-3E slice resources

Hi all,

I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and FDE inside single slice (SLICEM) anyway ? My initial understanding is that it has 2-SRL16E and 2-FDE inside single SLICEM.

My design have 2-SRL16E and 2-FDE. The XST said that my design would need : Number of Slices: 1 out of 4656 0% Number of Slice Flip Flops: 2 out of 9312 0%

That's weird for me, since I thought I'd need 1-slices only.

Could somebody help me ?

Thank you very much

Regards,

-daniel

Reply to
kunil
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Until the part nears capacity, par tries to put things in separate slices. But the best way to see what the software has done is to open it with fpga_editor.

Alan Nishioka

Reply to
Alan Nishioka

There are restrictions on whether an SRL can pack with a register. Since you specify an FDE, you *should* have those restrictions basically taken care of; the SRL write enable and register enable are different signals and the FDE doesn't use a reset.

It may just be the tool chose to spread things out. I've had to use the RLOC or other constraint to pack my output registers with my SRLs at times. The tools don't always make the "best" decisions but you can usually get them to do what you need in the critical paths through further constraints.

Reply to
John_H

Hello,

What you expected is what the report said. I think you may have misunderstood it. It has used 1 out of 4656 slices. The "Slice Flip Flops" count is count of how many flip flops were used in your 1 slice. The report could be a bit more clear, I think in the mapper report, this relationship is more obvious due to the use of indentation in the text.

Eric

Reply to
Eric Crabill

Reply to
kunil

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