Spartan 3E intefacing for dummies

This one??

One possibility is to add a 5V tolerant buffer chip that works with 3.3V (LVTTL), which has the benefit of speed. Another one is the resistor one which for most cases are likely to be the most overall effecient.

You can buy a simple chip packaged array of resistors to make sure nothing will overload the Spartan-3E.

I suggest you have a look at the schematics of different developer boards. They often show how things should be done.

Hello,

Just so there is no confusion, you cannot directly apply 5V to the I/O of any memeber of the Spartan-3 Generation. You should evaluate the input and output switching specifications for the devices you want to interface. In some cases, you may be able to do direct interfacing but for all other cases, I recommend you use level translators.

I found

a useful reference. There are many vendors with similar products, but I found TI has done a nice job of discussing the topic and made it easy to find all of the technical collateral. Please note, this is a personal recommendation and not an endorsement from Xilinx.

I see a lot of people using this series resistor "trick" to achive compatibility between 3.3V and 5V devices. You have to be very careful with this technique, it will only work with devices that have I/O clamp diodes and even then, the selection of the resistor value has to be computed based on parameters in the device datasheet and IBIS models. The resistor values will be different for Spartan-3 and Spartan-3E devices. Further, this technique is totally invalid with Spartan-3A, Spartan-3AN, and Spartan-3ADSP devices, since these devices use a floating well in the I/O design and do not have clamp diodes to VCCO (except for a programmable clamp in PCI modes; this clamp is normally OFF).

Eric

When using the series resistor technique there are also a couple of other considerations. Firstly, you need to make sure that the input FET gate can actually withstand 5V without breaking down - in other words, it is the maximum current and not maximum voltage that makes the pin non-5V tolerant to start with. Secondly, you need to make sure that the power supply powering the I/Os (or more particularly the clamp diodes) can sink current. If it can't you need to add a resistor from power to ground.

l

=A0The

e

le

.

I was not too keen to jump onto this unpleasant subject, but I must correct David: The basic issue is to avoid excessive voltage on the input, and the external resistor, together with the internal clamp diode (together with a power supply that can absorb current) does just that beautifully!. So the chip input never sees a voltage higher than Vcc +

0.7 V diode drop. You can easily measure this. The secondary issue is the amount of current, if the resistor value is too small, or the excessive delay if the resistor value is too high. And all of this only works if there is a clamp diode to Vc (and the supply can absorb the current, especially from many pins). We just hope that 5-V soon becomes a relic of the past, same as 12 V became obsolete long ago... Peter Alfke, Xilinx

Giuseppe

We use bus switches for this type of problem. Have a look at the schematics for our obsolete component replacement family Craignell

where we have exactly this problem where we need to make a Spartan-3E to be 5V tolerant but also need to achieve 5V CMOS levels on outputs to the outside world.

John Adair Enterpoint Ltd.

I

First of all thank you all for your answers.

Yes, maybe this pdf explains better the FPGA part (it has an ARM also):

It says it is a Spartan XC3S500E (speed grade -4) in a pq208 package. Very nice board, I am already able to talk with the FPGA thru the USB2.0 with a Delphi program. This was my major concern, I wanted a easy way to exchange data with the pc, and so far I was right.

Curious, I was writing a good idea could be to use the PCI bus interface of the Raggedstone (QS386PA), I guess Craignell uses a similar one (QS32X361?) .

If I understand correctly, they should work bidirectionally, or it seems to good to be true? Bidirectional, automatic, zero delay...

There are just two drawbacks for me:

1) I need to find them at reasonable price in Italy in low qty

2) I need to build a smd pcb (no DIL package I suppose)

Other than this they should solve my problem, no messing with resistors and currents bla bla.

Giuseppe Marullo

. .

Ie DTL/RTL logic?

also):

Perhaps something more conventional, like a 74LVX3245?

The simplicity of the IDC part is irresistable, no OE and no direction pins, no added delay, really neat.

Sorry Peter - I was confusing the subject by going beyond the OP's Spartan 3 discussion. What I was trying to say (not very well!) is that if you are going to try and limit voltage with a series resistor then you need first to ensure that there is a high-side clamp diode. Obviously if there isn't, the gate will see the full voltage and the input transistor may be compromised.

Most designs have protection diodes for each signal to ground and VDD. This limits the maximum voltage applied to the pad from -0.6V to VDD+0.6V. If the current is sufficient the voltage may go a little bit over VDD+0.6V.

FPGA may not be protected like that check the datasheet.

With respect to VDD_CORE. As an approximation the breakdown voltage is

10*gate length (in um). Hence 130nm will operate at 1.3V. Be clever design and process you may get a little bit more possibly 1.5V. Beyond the design/process limit the device will fry itself. You may have a margin of 10%. The maxcimum safe voltage is usually in the datasheet as abcolute maximum voltage. Even this may cause damage if spplied for any length of time. So the datasheet gives a min and a max stick to it.

Pad ring VDD may be higher. Possibly 3V or higher. They generally use a thicker gate oxide which will tolerate higher voltages. The datasheet will quote a min and max for this supply as well. Stick to it.

It may be a bit off-topic, but could someone explain how exactly a few extra volts can damage the GATE of a MOS transistor in the absence of protection diodes? I ASSume FPGAs use MOS technology. And the gates are insulated by the oxide layer. And it takes a lot more than a few volts to cause a breakdown.

-Alex.

Alexx, the breakdown voltage is of course determined only by the gate oxide thickness, but for practical circuits, the thickness goes together with the gate length (not logically, but practically)

When really thin oxide is 15 Angstroms =3D 1.5 nm "thick", then 3 V across it is equivalent to 2 billion volts per meter, or 2 million volts per mm. Would you want to touch a flimsy 1 mm glass plane when somebody puts 2 MV on the opposite side? I would hesitate... Peter Alfke

I understand perfectly what happens WITH the protection diodes. That's why my question includes "in the absence of the protection diodes" clause.

Could you be confusing the GATE BREAKDOWN voltage with some other parameter? The GATE BREAKDOWN voltage should be a function of the SiO2 layer thickness rather than the gate length.

I do respect the data sheets, especially the "absolute maximum rating" part :) So I fried my semiconductors by other methods...

I'm just trying to understand the physics of the issue.

-Alex.