Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?

On the Spartan-3E, LVPECL is input only!

This may contribute to why you find no 3.3V compliant standards in the data sheet.

The issue of running 2.5V standards at 3.3V reliably really should be taken up directly with your FAE rather than with this newsgroup. If it were a "sure, yeah, anyone can do it" issue, wouldn't the parts already be characterized that way?

The 3.3V LVPECL standard's last foot in the Spartan series was the Spartan-IIE. The Spartan-3 tried an LVPECL_25 version that wasn't continued into later parts. Odds don't look good in your favor.

Right, the supported output is "LVDS_25". I suspect that the outputs "want" to be symmetrical around VCCO/2, which is the 1.25V VCM of LVDS_25. LVPECL has a different common mode voltage.

Agreed. What I'm not clear on is what changes are made to the output structure to shift things around. Presumably, a stronger pull-up device and weaker pull-down would give the needed behavior, but I wonder if this couldn't just be done with a resistor network, assuming the swings are sufficient?

We're trying to replace a Spartan-IIE. In that device, the differential outputs seemed to swing rail-to-rail (I think), and you just controlled the output swings and common-mode with output resistors if needed. I'm wondering if I can do this here?

Or does the Spartan 3E really control the swings internally?

One last thought...

Can I simply program the two pins of a differential pair as single- ended LVCMOS_33, and just drive one with an inverted signal? The full- voltage output swing does not bother me at all - five resistors (two up, two down, one across) will get me to LVPECL_33 levels. Only issue is whether I'm taking my chances with skew between the outputs.

Using external resistors is the usual approach to differential outputs where the chip doesn't support your standard directly. Lattice parts use this for LVDS as well as LVPECL on some outputs. The issue of output skew is more important, however. If your outputs are clocked in the IOB flip-flops, the skew between two outputs in an IOB pair is negligible. If the outputs go to the pad from a fabric register, possibly via logic (inverter?) you'll most likely run into too much skew. I don't know if you can use the direct differential path between the IOB's in a pair unless you use one of the differential standards.

HTH, Gabor

Along with Gabor's comments, the BLVDS_25 differential output maintains the Spartan-IIE style of full-swing output requiring the familiar resistor network to get the appropriate drive levels. You can have the rail-to-rail

2.5V outputs but with a lower bandwith than the native limited-swing differential standards.

Hi John, Maybe, maybe not. Xilinx are only going to charactarise things to a proper spec. LVDS outputs are symtetrical about 1.2V ish, so they'll charactarise for LVDS with Vcco = 2.5V. I bet the outputs work fine with 3.3V Vcco, but then the outputs aren't meeting any published standard for Xilinx to charactarise against. However, this might well be good enough for someone's application, especially now modern LVDS receiver parts generally have a very wide common mode range. It could help out the OP who is understandably peeved about the bank requirements. Of course, you're quite correct, the FAE needs to confirm all this. Cheers, Symon.

We're not trying to break any speed records here, just need the speed and noise suppression of a differential signal to outside logic. The Spartan-IIE design we're replacing worked just fine. Is there published info that confirms BLVDS_25 uses full-swing outputs? I couldn't find any mention of this in the Spartan3E datasheet, just "figure 72" showing a resistor network for testing.

I actually prefer full-swing outputs so I can tune my swings and common mode with resistors - one of the outputs is not going to logic, but to a differential current-steering transistor pair. I could tell you why, but then I'd have to kill you all...

Thanks for all the replies - guess I'll try to get in touch with an FAE on this to get the "definitive word".

Is there any published info that confirms the pre-Spartan-3 LVDS outputs (which need the resistor networks) are full swing?

You can probably find the full-swing information only in the IBIS files where the information isn't spelled out too clearly for the casual reader. The info should be there, though, hard to interpret as it may be.

For doing any cute resistor tricks to get anything except LVDS levels out of there, it might be handy to use IBIS simulations making that model a valuable resource.