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Spartan-3E 500 and PCI 33/66 design

Hello, ALL!

In our design we are planning to use Spartan-3E in PCI 33/66 environment. We have developed our own PCI core. Since the code is completely RTL and does not have any platform-specific features we were able to test it with existing Altera ACEX-1K PCI33 board. Running on speed grade 2 Altera ACEX-1K device our core has about 1.5-2ns out of

7ns Tsu margin and even more for Tout. Now for production design we are planning to move to Xilinx Spartan-3E 500 FPGA. During detailed investigation of FT256 package we found several strange pins, marked as IRDY1, TRDY1, IRDY2 and TRDY2. Do these pins have any significant meaning for PCI designs? Unfortunately, I did not find any explanations in Spartan-3E datasheet, neither in accompanying application notes.

With best regards, Vladimir S. Mirgorodsky

Reply to
v_mirgorodsky
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schrieb im Newsbeitrag news: snipped-for-privacy@v46g2000cwv.googlegroups.com...

there is undocumented PCI_LOGIC primitive in S3e, so the special pins should be used with that special primitive. there is no official info but several people/companies have 'reverse engineered' the PCI_LOGIC and are actually using it (or able to use it)

Antti

Reply to
Antti Lukats

Hello Antti,

and thanks for your response. So, that seems that I will not have any advantages using those pins in my design :( I was hoping to avoid whatever floorplanning stuff during migration to PCI66, as I did for PCI33. Is there any possibility, that Xilinx will disclose functionality behind those pins in the future? Is there any recommended layouts available for PCI33/66?

With best regards, Vladimir S. Mirgorodsky

Reply to
v_mirgorodsky

Look with google groups for that subject. There was an interesting discussion November 2005.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Vladamir,

The PCI application has odd timing requirements. As a consequence, to be sure we can always meet the requirements, Xilinx has at various times had hardened bits of logic "just in case" the final silicon was not capable of meeting a particular PCI requirement.

If you would like more information, please email me directly.

Since these pins are undocumented, looks like there were not needed.

I am not in the Spartan Design Team, so I will go reseach it further if you need. The Virtex Design Team has done this also (at various times), so it is nothing new.

Aust> Hello, ALL!

Reply to
Austin Lesea

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