Spartan 3 Readback

I am working on a custom configuration controller that configures a Spartan 3 through SelectMap and verifies the configuration through readback.

Configuration is simply writing the .bin file into the S3, no problems there.

The trouble starts when I want to give the readback commands the the FPGA - al commands are ignored completely, even though I am using the same code to write to the device. I'm currently just trying to issue a SHUTDOWN command to the FPGA, to see if anything happens.

I've checked (and rechecked) that the data appears on the D0-D7 pins of the FPGA (byte swapped), with CCLK merrily running along, CS_B=0, RDWR_B=0, and I set persist=yes in bitgen.

The S3 datasheet has an interesting flowdiagram (fig 23, p37) that show reconfiguration starting with "prog_b low after power on", then "prog_b high" to avoid clearing the configuration. What is happing there?

Is there anything I'm missing? Some command (on CS_B/RDWR_B perhaps?) that will make the FPGA aware of my intentions?

Any suggestions will be greatly appreciated.

jvdh

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Reply to
jvdh
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Which Spartan3 device are you using? There is an eratta for the XC3S1500 stating that some of the engineering sample parts have a readback bug in them. You might want to search the Xilinx support website for readback failures, or consult the eratta pages for the device you are using.

Dan

Reply to
dand2k

Is there a workaround .. ?

Reply to
pbdelete

The workaround is to use production (non-ES) XC3S1500 parts.

Reply to
Eric Smith

hum, lasted time I checke the readback was not available on any S3 production silicon at all due to wafer bug. has it really been fixed now? If so then its a good thing of course.

Antti

Reply to
Antti

Dan:

Using a production XC3S200-FT256-4C on a Digilent Spartan 3 starter kit, nothing funny, hundreds of them must be in use out there... I haven't found anyone complaining that they can't do readback on them, but not many people are doing readback on S3s (apart maybe from the Xilinx Rosetta program)

thanks

Reply to
jvdh

Antti: That is scary, to say the least...

I found the errata stating that all parts for GQ fabrication process and date code prior to 0532 do not supprt readback of any nature (SelectMap and JTAG).

Now I'm just trying to decypher my part number...

Reply to
jvdh

I was scared too, a while ago. the errata looked like the issue is not going to be fixed at all, but ASFAIK Xilinx is committed to eventually fix the S3 readback on all production silicon from the new wafer/fab

antti

Reply to
Antti

According to the errata, my AFQ device should not be affected - which makes sense because my JTAG readback is working fine.

I've just realised that I can command the FPGA to shutdown (without losing configuration, this is one of the first steps of readback) after I've verified the configuration using JTAG.

So I presume the startup sequence at the end of the JTAG verification is slightly different from the startup after initial configuration.

Has anyone seen anything similar before? Or knows if the JTAG commands differ from those in the binary readback file?

Reply to
jvdh

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