Spartan-3 PQ/TQ/VQ SSO guidelines

Brian,

A few hopefully useful comments below,

Aust> Following up on this old thread:

Yes, long in coming, it is good to have SSO guidelines. More below.

The guidelines let a designer know when too many IOs switching will either cause an adjacent output signal to falsely assume the wrong state (bounced to a 1, or to a 0 when it was a 0 or a 1), or when an adjacent input that is quiet is bounced into the wrong state. In almost all cases, the LVCMOS input levels for a 1.5V LVCMOS input is the worst and most sensitive input, as we must assume that you may have a 3.3V IO bank adjacent to a 1.5V bank, and may have the worst case combination of victims and aggressors. You may need to have even more margin, or you may not need the margin suggested, depending on the IO standards and voltages chosen.

SSOs also affect (cause) the jitter on data and clock signals, so any design with little or no margin becomes incredibly sensitive to SSOs.

Jitter, is the end result of all sins of poor, or no SI engineering.

We also have to assume some kind of series inductance for the customer pcb for ground and power pins. If it is less, the performance is better. If it is more, the performance is worse. I believe we assume

500 pH for each power and ground (1uH total in the power and ground circuit series L from the PCB).

If the package is 300 pH, then the contribution from the package is not much. But, if the package is another 1 uH, then the ground bounce almost doubles! Hence the reason why these packages are not well suited to anything that creates di/dt (see next comment in line). Slow attribute IOs, LVDS, low current IOs, are all much friendlier (to the package and its environment).

The added package inductance for these packages leads to this obvious result. As Lpkg got larger, V = -Ltotal * di/dt got larger, too.

This is only true if the driver is driving a true differential load (NOT two separate 50 ohm signal leads!!!). As most differential trace runs are not perfectly balanced, and not perfectly differential (they have coupling to ground), we also have to start assuming standard pcb trace routes are used....

Sort of like saying: "we are ususally OK, but some folks have had a less wonderful experience, and maybe if you have a lot of them, you should simulate the SI." Not much different that my usual stance: simulate, simulate, simulate.

No, the S3 differential IOs are quite the same as V2 and V2P.

Answer records are not automatically corrected when things change. They get reviewed on a cyclic basis (they in effect 'time out' and have to be reviewed). Even when an answer record 'times out' it is not always caught as being out of date. I will forward this to the group involved. There are over 10,000 current answers ....

If you have a question about an answer record, please send it to the hotline (or post it here). They are quite excellent at keeping track of a massive amount of information, and also keeping it up to date.

Thanks!

Hi Austin, Just goes to show those lead frame packages are history! One small point, in the excerpt below you say that LVDS pairs have trouble if they're "not perfectly differential (they have coupling to ground)". Assuming the Xilinx LVDS outputs are truly differential, my opinion is that as long as each one of the pair is identically coupled to ground, or indeed to any other plane, there shouldn't be a problem. In other words, the coupling to ground shouldn't, per se, cause a di/dt power supply event when the output switches. Of course, if the pair isn't perfectly symmetrical (perhaps due to the lead frame?) there will be a net power supply current change when the output switches. In fact, where you say "NOT two separate 50 ohm signal leads", I disagree. Each pin of the pair should be able to drive separate independent 50 Ohm lines with no di/dt problems, provided these 50 Ohm lines are identical in characteristics. (You could AC couple the lines to overcome any DC termination non-linearity issues.) How could the LVDS output 'know' it wasn't driving a 100 Ohms differential pair rather than two separate 50 Ohm ones? Best, Syms.

Symon,

Well, this needs some explaining. Maybe we are in agreement?

See below,

Aust> Hi Austin,

The LVDS driver consists of a source 4 mA, and a sink 4 mA source that are switched by a 'tree' of fets. If these were perfect current sources, then their impedance would be infinite. Since they are not perfect at DC< and certainly much less than perfect for AC (capacitance coupling), they are only as good as the best the technology can deliver

- which is not all that wonderful.

In other words, the

So, just due to the imperfect current sources, and the capacitive couipling, you get imbalanced DC currents. Additionally, there are pre-drivers which must drive the larger switches, and these are also generating single ended return currents.

there will be a net power supply current

No such thing. Hence the more conservative warning. I have never seen anything perfect yet. There is always some mismatch.

(You could AC couple the lines

By measuring the common return currents. If I drove a 100 ohm twinlead straight up off the pcb which was termianted in a 100 ohm resistor, I guarantee I would see different behavior than if I drive two separate 50 ohm lines, only because there is no such thing as perfectly matched 50 ohm lines.

Unfortunately, 100 ohm twinlead is not a very common application.

Forcing an AC balance by coupling the + to - together only works in the ratio of the imbalanced C to the forced C -- as well as ruining the edges on the channel.

That would be 1 NANO-Henry, not 1 MICRO-Henry, from 2 x 500 pH.

External lead inductance of only 500 pH is real good, when you need to use a via to get to an internal ground plane. I think you need to use microvias in the pad to keep it this low.

Jon

Jon,

OOPS. Yes, 1 nanohenry (1nH) total power loop inductance for the pcb loop.

Now, there are more than one power and ground pin for an IO bank, so this also has to be taken into account (the numebr of pins in parallel, and how effective they are).

Austin

J>

The point of my "Bad News" commentary was to highlight to other designers that the new SSO guidelines mean these parts can often only use a small percentage of the available I/O pins as outputs.

For me, it's equally "obvious" that the big leaded parts really need to have more pwr/gnd pins per bank - do "virtual" pwr/gnd pins created with a high strength driver count the same as normal pwr/gnd pin pairs for SSO calculations?

I'd love to have participated in the design review where it was decided that 2-4 output pins per bank for most standards was an acceptable design target for the leaded S3 parts :)

My own wish list for hypothetical "Spartan-3E" (sic) leaded parts:

- ground paddle packages with GND S+ S- GND(VCC) pinout

- implement _DT differential terminators

- remove DCI ( hopefully improving Cin )

- better slew rate control options for output drivers (instead of DCI)

Thanks, that's good to know.

So it's just the differential net loading balance assumptions used in the SSO calculations that have changed, not the drivers themselves.

( One trick I've used to damp out the input Cin reflection when there's plenty of drive signal is to stick a differential attenuator ahead of the receiver; the same idea should also work at the driver to let it 'see' a more perfect load. Panasonic makes some nifty 100 ohm differential attenuators in a tiny [0404] package, stocked by DigiKey. )

combinations.

Spartan-3."

less

How do you propose that the end user simulate on-chip SSO problems created by unbalanced loading on an LVDS driver?

AFAIK, the the current generation of Xilinx IBIS models, when used with presently available IBIS simulation tools, can not model on-chip SSO related supply problems for differential I/O standards.

Perhaps if all 200,000+ user seats of Xilinx S/W also bought a copy of HSPICE to use the encrypted SPICE models, they too could attempt to model on-chip SSO for a particular differential pair routing topology...

Off to buy some Synopsys stock, Brian