Spartan 3 pinout typo?

You are correct. The pin name and pin number in the data sheet is correct as is the PQ208 footprint diagram. As you described, the "_0" suffix indicates that the pin belongs to I/O bank 0.

The mistake in the data sheet is strictly the bank indication in the pinout table. This is being corrected as I write and should be posted on

by no later than early next week.

Please accept my apologies for any inconvenience this might have caused.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

The Spartan-3 pinout tables have now been updated to correct this mistake. The mistake in the data sheet is strictly the bank indication in the pinout table. The pin name and pin number in the data sheet is correct as is the PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)

Spartan-3 Complete Data Sheet (All four modules)

The electronic ASCII-text footprint tables were not affected by this mistake.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I realize that there are some issues with IO that I am not sure how to resolve. To get an understanding of how to approach the problem I need to know what IO pads and pins are mapped to what CLB columns. I am looking at using the XC3S400 in the 456 pin BGA package. Where can I get info on how the IOs are mapped to the CLB columns?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Steven-

Thanks for the quick response. It seems you corrected the other (similar) bank indication problems. It didn't matter much, but was a bit confusing at first.

Jake

The relative location of pins to CLBs can be seen graphically in PACE or put into a text file using "partgen -v xc3s400fg456"

-- Marc Baker Xilinx Applications (408) 879-5375

into

I think you have a leg up on me. I am not familiar with a program called PACE. I am guessing that is the chip editor? If so, I do not currently have the full ISE tools and so do not have the chip editor. How else can I get this file?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Hi Mr. Collins,

I sent the complete file to your personal E-mail address.

If you have the tools, executing "partgen -v xc3s400fg456" generates an ASCII text file called "3s400fg456.pkg".

A snippet from the file is shown below, just to provide some context on the fields.

pin PAD2 B4 0 IO_L01N_0/VRP_0 X1Y63 115S

0 pin PAD3 A4 0 IO_L01P_0/VRN_0 X1Y63 115M 0

My apologies, I didn't see your original reply to the last posting on this thread.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

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