Spartan 3 Output Driver Issue

Hello All,

I have been having some trouble with a custom designed FPGA board based on the Xilinx Spartan 3 (XC3S400-FT256). I am hoping that someone here might be able to shed some light on the problem. Essentially, pins on certain IO Banks don't work as outputs unless at least one pin on the affected bank is designated as an input and is continuously receiving an active high (3.3V) signal.

First let me go into a bit more detail about the board and the FPGA configuration. All 8 IO Banks on the FPGA are configured to receive VCCO=3.3V. Every IO pin used is designated for LVTTL signaling. 40 of the FPGA pins, mostly from IO Banks 0 and 5, attach to a General Purpose IO header on the board. While attempting to program these pins for various output functionality, we noticed that they did not work (the output will always be logic '0') unless at least one pin on the same IO bank was specified as an input and was receiving a 3.3V (logic '1') signal. The problem appears to be isolated to banks 0 and

5, though it is possible that other banks may be affected.

When I look at the output of the non-working pins on an O-scope, I see that when the signal should be driving high to 3.3V, its only jumping

200mV or so. It's as if the signal is somehow being pulled down to ground, though I have no idea how or why. The 3.3V VCCO supply appears to be fine, and is connected to all of the pins on the FPGA that it should be. Other components on the board are also powered by the 3.3V supply, and they are working fine.

I'm pretty stumped as to what might be causing this problem. Has anyone out there ever experienced this problem? As far as I can tell, it certainly isn't a "feature" of Spartan 3 FPGAs. Any help would be greatly appreciated.

Thanks,

-Ben

Reply to
bengineerd
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This screams that the Vcco for the bank isn't actually powered. The input pin's protection diods kick in to provide the Vcco to the rest of the bank as Vin-Vdiode. It's quite possible you have soldering problems that are causing issues with the Vcco balls on those banks.

It all makes solid sense for non-powered I/O banks. Do you have more than one board? Do you have access to the layout? If there are direct plane connects for power but not for signals, there could be differences in the soldering for the different pin types. Good luck.

Reply to
John_H

John,

Thanks for the reply. I agree that it would appear that the banks are somehow not being powered. We have two boards based on this design, and they both suffer from the same problem. It seems strange that both boards would suffer from the same soldering anamoly. The folks who did the layout and routing have gone back and checked the connections to VCCO, and everything seems to check out.

Can you elaborate a little more on this? How might the soldering be different? I believe the power pins do have direct plane connects.

Thanks,

-Ben

Reply to
bengineerd

Our process guys were very uncomfortable with any inconsistent thermal footprints for any FPGA balls in our reflow setup to the extent that they wanted all balls connected to via escapes, necessary or not; that certainly didn't work for me for the outside rows but I understood their point. Depending on how the part is assembled onto the board, the balls connected to vias that feed traces have a low thermal load - when heat is applied, heat is transferred efficiently. The balls connected to vias that connect to planes through thermal releiefs have reasonable thermal transfer efficiency because heat transfers to the balls with little dependence on the plane temperature, but some. The balls connected to direct-plane vias have most of their heat transferred directly to the plane leading to very poor thermal efficiency.

Preheating the board can bring the internal plane temperature high enough that the impact on thermal transfer efficiency is minor. A hot-air BGA rework station will typically have the hot-air head on top responsible for most of the soldering but a hot-air head on the bottom as well that's used to preheat the board before the top is brought to a temperature that will melt the solder. Without the preheat, there will be failures. Lots. Epoxy-glass is a thermal insulator. Planes need to heat up through the exposed copper connections and the epoxy-glass. It takes time to get to temperature.

Different reflow methods have different requirements to get good process yield. In a well-tweaked process it shouldn't matter if there are direct-connects to the planes or not. If the process is even a little sloppy, the direct-connections can sincerely degrade process yield.

There are shops that offer reasonably-prices xray inspection that should expose any soldering faults. You can even find a shop on eBay (based in AZ?) that offers a $50 service - search on "xilinx xray inspection" and you'll find the eBay store listing.

One test that might produce results: use a diode checker on your unpowered board's I/O pins. If the protection diodes are engaged when the device is off and unconfigured, you should see the diodes for the I/O pins to the VCCO of the associated banks. My S3E starter board shows about 0.4V on the I/Os I probed with the doide-checker (standard DMM function) COM/black on the VCCO pin (there's a jumper for 3.3V/2.5V so I know it was unconnected) and the V/ohm/red lead on the I/O pads. If your VCCO is unconnected you should see no-connects or simply much larger values (typically 1.2 V on my board) from other circuits. COM on floating VCCO plane - 0.4V, COM on 3.3V plane -

1.2V, COM on 2.5V plane - 1.2V. Connect the plane to the VCCO and the 0.4V is seen from the voltage plane to the I/O.

Happy hunting!

Reply to
John_H

Thanks for the in-depth description. I went back and checked, and all balls are connected to escaped vias. There are no direct plane connections. When we got the board back from the surface mount shop, I was told that they had X-ray'd the boards and they had both checked out. I will preform the test that you describe to see what that reveals.

Thank you again for your help.

-Ben

Reply to
bengineerd

A quick caution: I/Os that are connected to other chips with the same supply rail as the VCCO may give a false "connected" reading if their protection diodes kick in but the FPGA's I/Os are left floating. The quick test I did on the starter board was with unconnected I/O pins (signals brought out to headers).

Reply to
John_H

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