What you can do, though, is play with the thickness of the prepreg. Make it thin enough and you increase the capacitance between ground and power planes. Not to a very high value, granted, but connected to the planes by a _very_ low inductance!
- Brian
Oops, I missed that explanation when skimming XAPP475 yesterday to find the TLine parameters.
I was actually thinking of this sentence from Answer Record #19320 when I griped about Xilinx still using IBIS 2.1:
"We do not have an IBIS model for LVDS_25_DT, as the IBIS specification does not provide a mechanism for representing the true differential termination"
It's been I while since I read the IBIS specs, but I believe it was IBIS 3.x which added support for modeling a differential terminator, instead of having to bury single-ended terminator currents in the GND/VCC clamp table.
My interest in having data available in one of the newer IBIS versions is not to actually use them in an IBIS simulator, but to have {almost} human-readable documentation of the differential package and I/O parasitics, which Xilinx doesn't currently publish in any other form.
I suspect if you use the differential I/O standards, and then tie adjacent I/O pins as strong drivers to GND(VCCO), you can establish a nice GND S+ S- GND(VCCO) pinout in a leaded package and have a good shot at doing extremely fast I/O in an el-cheapo package.
And I'd love to see a small S3 sold in one of the enhanced VQFP ground-paddle packages, for both thermal and electrical reasons, especially if done with a G S+ S- G pinout.
As were yours, thanks - I've been building 4-6 layer boards with FPGA's powered from localized plane fills, as you describe, for many years and generations of FPGA. Keeping the 'dirty' FPGA power plane localized in such a fashion also helps in RF/mixed signal board layouts.
I took a look at building a simple first or second order SPICE package model of the leaded S3 parts a few months ago, but there wasn't any package data available in the IBIS files; if I get a chance to take another crack at it, I'll post some LTspice files.
And if anyone out there has built a test fixture and made either differential TDR or VNA measurements on some of the S3 leaded packages, I'd love to see some real world data to help model the pin-pin coupling for a G S+ S- G pinout :)
Brian
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