spartan 3 on 4 layers

Hi guys

I have just finished routing a simple board with a 208 pin qfp spartan

  1. I have just used top and bottom layers and it is time to add the power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and vccaux. I have not routed any signal under the spartan on either layer so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the bottom layer.

Just wondering if anyone can see any holes in this idea.

thanks

colin

Reply to
colin
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Colin,

Our SSO rules assume you have dedicated planes for Vccint, Vcco. If you do not have both a power and a ground plane for each of these supplies, the SSO numbers must be reduced. This also goes for simultaneously switching CLBs, and not just IOs. We assume a power and ground plane (yes that would be four layers just for power) for low inductance on the Vccint/Vcco.

You might want to investigate the Point of Load concept (POL or POLA) from TI (US) and Belkin (Japan).

By placing power supplies directly at the load, the loop inductance is greatly reduced.

I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very well. Perhaps you pay more for a more capable power supply, but you pay less for the PCB.

Remember that V=-LdI/dt. There is no way to reduce ground and Vcc bounce without reducing either the I (current switched by reducing the number of things switching), or reducing the L (indutance). The time (dt) is not something that can be changed (as in internal nodes switch time is fixed by process and design).

No amount of bypass caps will fix a bad pcb.

Aust> Hi guys

Reply to
Austin Lesea

Colin, It's hard to answer this question without knowing what the FPGA is doing. If the I/Os are switching slowly, but the logic inside is going very fast, then your Vccint supply is of paramount importance. For example, if all the slew rates in the IOBs are set to slow, the 3.3V rail maybe doesn't need to be on a plane. In fact a crappy Vcco can sometimes actually help EMI problems by slowing the IO signals. I'd say that as you're using a PQ208, high speed stuff isn't foremost in your mind. When Xilinx say that 'all the supplies are recommended to be on a plane', what I guess they mean is 'we tried it with all the supplies on a plane and it met ALL our specs'. They're not saying other methodologies won't work, especially if you're not trying to meet the fastest switching rates. Although wire-wrap's probably a bad idea! What you can do is what I think you're suggesting, have mini-planes for each supply, sharing the PCB layer. If you can also get some 0402 caps on the top-side (fpga-side) of the board very close to the pins, that'll help a lot. With the package you're using just go for the biggest value X5R cap you can get, 1uF probably, and route it on the top layer straight to the pins. This takes the via inductance out of the equation. Don't worry about all that 'use several different values to widen the resonance', that's probably mumbo-jumbo in the real world, especially with a PQ208. There are too many parasitics around to confuse the issue. Small package (=low inductance), big capacitance is what you want! The point-of-load supplies Austin mentions are a good idea, but don't bust a gut getting them close to the FPGA, just make sure the supply rails have very low AC impedance near the FPGA. So, lots of point-of-load decoupling and lots of copper is what you need! If I were you, I'd be optimistic. You're thinking about this, which gives you a much, much higher chance of success than some folks... Good luck, Syms. p.s. More reading:-

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Look at 'Bypass Capacitors'.

"colin" wrote in message news: snipped-for-privacy@posting.google.com...

Reply to
Symon

This is a very curious statement. Bypass caps provide virtually all of the high frequency current-they get recharged by power supply. Granted, you need low impedance to recharge the caps before they are used again, but the power supply is not supplying the fast edge currents.

Reply to
Tom Seim

..but if your PCB puts too much inductance between the caps and the FPGA, this 'bad' PCB won't be fixed by merely adding more badly routed and positioned bypassing. Cheers, Syms.

Reply to
Symon

I think he was addressing the comments about keeping the PSU near the chips. I have *never* heard anyone recommend that PSU placement would affect the need for good PCB design. The range of frequencies that PSU selection or placement would affect is way below the range of freqencies that would be affected by PCB layout. I don't think anyone here is talking about putting ceramic decoupling caps an inch from the chip pins.

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Reply to
rickman

Tom,

There is no "C" in Ldi/dt.

If you can find out how varying a capacitance in any way changes the induced bounce (V=-Ldi/dt), let me know.

Bypass capacitance prevents rail collapse, but it does nothing to prevent ground bounce (it can actually make it worse, as there is more energy stored which makes di larger and dt faster).

Aust>

Reply to
Austin Lesea

[snip]

I think the point being made here is that bypass caps located where the inductance between the caps and the chip is small, the i in di/dt *is* significantly altered if the i being discussed is power/ground plane inductance.

The regulator at the load should only help out if 1) the regulator has extremely fast response or 2) the current demands fluctuate at very high aplitudes at much lower frequencies.

The designer *must* keep in mind the effect of a sudden increase in current on the total available charge from the bypass caps locally. If the step-increase in current deflates those bypass caps beyond the voltage tolerance of the target device, very bad things will happen. It's better to overdesign the bypass caps (rather than relying on the minimum operating voltage of the chip) because of other effects like induced jitter.

When the bypass caps do their job in the frequency range they're designed for, the lower frequencies still need to be accommodated. That's where the regulator takes over. With a response in the 10s of microseconds, a good regulator won't have a problem delivering the change of current where the bypass caps are starting to lose effectiveness.

If there are inexpensive regulators with 100s of nanoseconds respons time, I'd be paying closer attention to a distributed power delivery approach. I took a quick look at a some LDO regulators which - while claiming to have "fast transient response" - give no actual data on the recovery time. Is it worth a 500 mV dropout into 1.2V to use an LDO rather than a switcher far from the chip with an appropriate bypassing scheme?

The "Point of Load" at ti.com comes up with a DC/DC switcher module where "the transient response of the DC/DC converter has been characterized using a load transient with a di/dt of 1 A/µs." While this appears to be a better spec than I originally figured (for available supply voltages down to 3.3V, not 1.2V yet) the location could still easily be a couple nanoseconds of board distance away (about 10"?) and not feel the difference in the transient due to the di/dt of the power plane.

If there is a "new, better way" to power our transient-rich designs compared to good - local - decoupling schemes, I'd be interested to read up. As long as decoupling is within 1/10 the wavelength of the capacitor's effective frequency on a zero inductance plane, the capacitor will do it's job. As long as the capacitor is not degraded by the plane inductance between the cap and the chip, the cap will do its job. If a cap is marginalized by an inductance, the cap will be less effective and some analysis may be warranted. The numbers whould be considered.

Reply to
John_H

The L di/dt issue is a red herring. Every good engineer knows that *NO* circuit is pure L or pure C or even pure R. All circuits are a combination of the three (hopefully linear) and what matters is the resulting Z.

NO regulator has enough speed to respond at the frequencies that power planes address. Even if they did, the required distance between the regulator and the chip would add L (increasing the Z) to a point that counters the feature.

...snip..

You are preaching to the choir now!

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rickman

Reply to
Symon

Reply to
Symon

Reply to
Symon

John,

See comments below,

Austin

Actually, my point is this: given some bypass arrangement, the ground bounce does not vary if you suddenly make all the byapssing 10X better (ie better caps, more farads). In fact, bounce may get worse because the rails are not collapsing (anymore) externally.

Agreed. On chip, the current demand is almost instant. By the time the local capacitance on die is exhausted, and the caps in the package are out of charge, and the immediate external bypass caps have also given up their electrons, the time of the current profile has been stretched. If a regulator is fast enough, it can help. If it is too slow, it can't.

The PCI/SDRAM card I have with the POL ultra-fast transient regulators was able to use 4 layers. Never seen anything less than 8 layers used before. Pretty clever designers for that PDS.

-snip-

I believe they have all the way down to 1.0 volt available now. Check with your TI disti. Belnix is adjustable with a resistor.

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(most of the literature is in Japanese, and I have received some recent English translations, but I am still at a disadvantage here....)

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Agree on all of the above.

The Belnix POL supply has a 50 mV MAX droop for a 5 ampere load change (step, instant load change). Looks like it never even saw the load change, except the IR drop happens and you see 50 mV change. They talk about a ~100 ns time to go from 0 amperes, to supplying 5 amperes with no overshoot or ringing of the output (beyond the normal switching noise and the IR drop of 50 mV).

Initially, I was a non-believer, like you. Basic rules were separate planes, minimize inductance, maximize bypass, etc. 1/10 wavelength back of the envelope rules, etc. Then I saw a 4 layer pcb with a POL regulator (actually, two, one for core, and one for IO) and very few bypass caps. I had never seen a working 4 layer pcb prior to that with PCI AND SDRAM on a 2VP20 (let alone one without a lot of caps). Just too much current needs to be switched for BOTH PCI and SDRAM, and the only other solution I had seen were two planes for Vccint, and two planes for Vcco, plus a lot of bypass caps (one per power ground pin pair).

Perhaps we are both over simplifying the problem? Perhaps is it more like a power transfer problem over a 2-D transmission line: the longer the line, the worse the problem? By shortening the line to less than 1" (25.4mm), the POL concept is a better solution? The output impedance of the power supply (an active and complex value) is reflected to the load and is kept at a much lower magnitude, which causes much less voltage fluctuation?

Reply to
Austin Lesea

Reply to
Symon

Reply to
Symon

Symon,

Answers below,

Aust> Austin,

It was about number of layers. A ground plane is a layer.

The ground L is the bounce in the ground plane. The Vcc plane L is the bounce in the Vcc.

I said a pair of planes for each high current switching supply, namely a Vccint/Gnd pair, and a Vcco/Gnd pair. That makes four layers. The dual grounds are required to reduce the ground return inductance to something that is reasonable. And the vcc loop inductance. Both.

It's easier to use this methodology, and certainly easier for

I disagree. Looking at those that succeed, vs. those who have issues, I see those that followed our recommendations a much happier bunch.

We take our recommendations very seriously. We are not out to minimize our support, but rather to maximize our customers' successes (and our own in the process). To suggest a marginal power distribution system is just not good business! Why would we suggest that a customer 'play around' when we and our disti's have already run all the simulations, and built numerous verification, characterization, and demo pcbs to prove what works, and what does not work?

Anyone who thinks they know better how to use our chip might get lucky, but often is not. Why would anyone think that they know more than we do about something they did not design? Surprisingly, many do think that they know more, and as a consequence are sometimes terribly disappointed.

For the introduction of V4, we had a 1Gb/s LVDS networking pcb ready to demo, and a memory interfaces pcb ready to demo. Those are two of the largest applications problems our customers face today - fast IOs and fast memories. If we don't know how to make it work, how would that make a customer feel?

I always read how a vendor suggests using their device.

The use of the POL supplies is an experiment to validate a concept. I wouldn't go to product until I had proven it works (if it was my job).

The same goes for using only four layers, or traces to Vcco, etc.

You can also use this layer

Yes, ground is all important (more so than the Vcc's), and Vcc 'planes' may sometimes just be routed. It depends again on the switched currents.

Yes, the rails don't collapse.

di larger?

Yes, the source impedance is lower.

dt faster?

Yes, lower source impedance also leads to faster transients.

Lastly, we had a case where the vias from the bypass caps where wired such that the L from the cap to the plane was the largest element (not hard to do, one tiny via each end, at the end of a flag of trace to the chip cap). Adding caps directly across the existing cap did absolutely nothing. One might conclude that the bypassing wasn't doing anything. But really, the L to the caps was so bad, that the caps were not doing anything. Little things count.

Had to tell the pcb layout person to get the L out of there! (excuse the pun - again)

Reply to
Austin Lesea

Go back and read the OP. He had a ground plane, he wanted to know if he could get away with routing the power separately. Yes he can! Especially with a PQ208 which has a lead frame made of little inductors on every pin! I hope you Xilinx boys have encapsulated some bypass caps in there somewhere!

(only!)

that

Assuming the ground balls/pins are connected straight to the ground plane and if the Vcc balls/pins are coupled tightly to the ground plane via sufficient decoupling capacitors and enough low inductance copper track/local plane, you don't need a Vcc plane that traverses the whole board. The current loop is between the ground plane, the FPGA, the bypass cap. One plane can't bounce without the other if the bypass caps nail them together!

and a

reduced.',

separate

little

Not necessary. The ground layer is important, as I said later more ground planes are good. But big planes for Vcco and Vccint are NOT necessary. Just low inductance from the bypass caps to the FPGA power pins/balls.

Maybe you could come up with better recommendations, then your happy bunch might get happier and richer from the money they save on PCBs!

Fair enough. I'm sure this is true.

Deep breath! I can see why you sometimes rile up Rickman! ;-) Anyway, I count myself as someone who does know better how to use the chip in this case, at least better than XAPP623, and I have plenty of boards to back it up. When you get lucky every time, there's another word for it. I'm not saying it's easy, but it's possible, and I save my company a lot of money on PCBs by using fewer layers, fewer bypass caps, and squeezing extra functionality onto the board. What I'm trying to do with my posts here is help other folks understand that what Xilinx says is only one way to do it; other ways work, and work very well. Don't get me wrong, I think Xilinx does an excellent job, especially at support. Your recommendations enable someone with little PCB design expertise to get it right first time. Sometimes though, we non-Xilinx 'gentiles' can do good stuff too!

We agree on this!

plane

the

OK, so now we agree that a routed/local planed Vcc works? You seem to flip-flop more than a Democrat nominee! ;-) Again we agree, local plane/ routed can Vcc work fine.

plane?

But if the rails collapse, ground bounce is the least of your worries. Your design is already dead.

At these high frequencies, the capacitor package size (= inductance) is the thing that dominates the source impedance. Not the capacitance. Look at the manufacturers data sheets. Download this and look for yourself

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. Above 50MHz an X5R 0402 cap has the same impedance whether it's 56nF or 470nF. The ground bounce problem is solely a result of poor coupling between the ground plane and the FPGA.

Of course, very good point. It's a constant fight against the PCB routing tool to prevent it stripping out extra vias I add to decrease impedance. Ah, Austin, I enjoy these chats. Even when I C your terrible puns! Write back soon mate, Syms. ;-)

Reply to
Symon

That seems reasonable, but it's awful short on specifics.

How big does the plane have to be? Are you assuming power/gnd pairs? If so, what spacing between the pairs? Which plane/pair needs to be closest to the chip?

Is there a procedure for computing the SSO rules given non-optimal power planes?

Wise-ass mode would be: What page of the data sheet describes the details?

Let's go at it from the other direction. What are the chances of making a solid PCI card on a 4 layer board? Assume a TQFP-208 package and assume that the PCI side is the major SSO problem and that the routing on the non-PCI signals is easy.

I haven't done it, but I think you can get a reasonable layout in 4 layers with a TQFP package. I'm assuming that the routing to the signal pins from the rest of the design is easy. (That's "reasonable" to my imagination/eyeball. Reality might be totally different.)

The idea is that the top/bottom layers under the chip are not needed for routing so you can fill them with copper to get a tiny plane. It's probably not big enough to do much good, as a plane, but it will be a solid connection for all the appropriate power/gnd pins and bypass caps.

It would be interesting to see how good that chunk of plane approach is compared to placing bypass caps right next to each pair of power/ground pins (with tight routing and fat traces).

I've got a cheap modem PCI card handy. Looks like it's only

2 layers.
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Reply to
Hal Murray

Hal,

For specifics, please read:

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SSO guidelines are on page 23 of:

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Austin

Hal Murray wrote:

Reply to
Austin Lesea

Hal, For this PCI card, I think the I/O will be your toughest problem. 32+ long traces at 33MHz. So, I'd consider this. Assume four layers, 1, 2, 3 & 4. FPGA mounted on layer 1. First, make layer 2 a ground plane. Underneath the FPGA on layer 1, fill the area with copper and connect to all the Vcco pins. Layer 3 under the FPGA should be copper flooded for Vccint. You now put a chunky C shape around the Vccint flood on Layer 3 to route Vccaux. Via Vccint, Vccaux and Ground to each and every required pin on the FPGA, but keep the vias inside the square of FPGA pins, to avoid hindering routing your I/O signals outwards on layer 1. Vcco vias can connect to anywhere on your layer 1 mini-plane under the FPGA. If you have more than one Vcco, you can divide up this mini plane, but try to group banks that share a Vcco together.

On layer 4 under the FPGA, pack with bypass caps for Vcco and Vccint. (Check XAPP623 for good advice on layout for bypass caps.) You need at least one via for the power end of the cap, more is better, don't share vias between caps. Flood the rest of this bit of layer 4 with ground for the bypass caps, and use many vias to connect this layer 4 ground flood to Layer 2, your ground plane.

Now, route your signals out on layer 1. Cram them together so that you can fit extra bypass caps onto layer 1, for each of Vccint, Vcco, Vccaux. As for bypass caps, use 0805s on layer 4. Use 0402s on layer 1. Via inductance is around 1.2nH, double the capacitor inductance, so don't worry about high frequencies on the bottom layer. In fact for a PQ208 the lead inductance is probably around 10nH, so don't worry about all that 'spread of capacitance values' crap, big capacitance is beautiful here!

Try it, you never know, you might be one of Austin's lucky ones! ;-) Cheers, Syms.

Reply to
Symon

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