Spartan 3 Mapping Problem

So, I'm busily poking around at a Spartan 3 design, and can't get my latest iteration of things to build properly. I've got all my pin locations defined, but make no recommendations to the tools as to which clocking resources to use how and where. Yet when I try to map the design, I get:

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ERROR:Place:1018 - A clock IOB / clock component pair have been found
that are not placed at an optimal clock IOB / clock site pair. The clock
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Rob Gaddi
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Are all your clock inputs defined as one edge of the chip? I'd suggest using FPGA Editor to delve into your chip to understand where the signals are easily routed from. It may be that you *must* go from one side to the other to use the pins you've chosen. I recall some suboptimal choices in the Spartan-2s that made me choose manually where my clock buffers and DCMs would be so I haven't come across the error you have lately.

- John_H

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John_H

Three of them (including the one throwing the error and the one with the DCM on it) are along the top of the chip (CLK4, CLK6, and CLK7 pins) The fourth is down on the bottom on CLK0.

-- Rob Gaddi, Highland Technology Email address is currently out of order

Reply to
Rob Gaddi

So are you going to look into the FPGA Editor view like I suggested?

Another question for you to ponder much more than to answer here: did you instantiate the BUFGMUX primitives or are those coming from your synthesizer? It may be that you need to hook up the I1 channel rather than the I0 on one or two of your BUFGMUXs to work with the routing from the clock pins to the buffers... which is why I suggested looking at the details of the part in FPGA Editor.

- John_H

Reply to
John_H

Rob,

Did you LOC your IOs down? Each BUFG has a dedicated IO that should be used. A list of these IO locations are available from the Spartan

3 User Guide. If you LOC the IO to one of the non-dedicated IOs, this error message will appear.

Marv> Rob Gaddi wrote:

Reply to
Marvin

Each of the clock signals is LOCed to a dedicated clock IO pin.

So I went in with the FPGA editor to do a little more investigation, and it sure looked like I could just pipe the clock signals from their points of origin to the proper BUFG with no problems. I tried LOCing them down in the UCF and rebuilding, and came up with the excitingly new error of:

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ERROR:Place:1023 - A global clock component 
configured as a selectable mux is placed in site BUFGMUX6. This 
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Rob Gaddi

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