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Spartan 3 FPGA verification via readback

Hi, I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. There is this strange behaviour of different bitstreams that made me to turn on the verify option while configuring the FPGA. It was quite disappointing that the verification for different bitstreams fail. The FPGA does get programmed successfully but does not pass the verification phase. I have started suspecting the FPGA part on my board. There are some ISE projects whose generated bitstreams work fine on the board but if I add some functionality in these projects, the FPGA stops responding or start misbehaving. Is there anyway I can verify the complete FPGA for its LUTs, static ram cells etc which hold the configuration bits? In case if some LUTs or ram cells are faulty, is there any way I can know the locations of these faulty cells so that I can try mapping my design on the working area?

Regards SMF

Reply to
maverick
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Before you get too far in suspecting the FPGA, take a look at your board. Is it capable of handling whatever post-configuration current surge your bitstreams generate? Since your bitstreams are failing when you add functionality, I would immediately suspect the added current draw from that functionality is causing a voltage drop on the core voltage rail. A sufficient voltage drop can cause the FPGA to lose its configuration.

- Nathan

Reply to
Nathan Bialke

The bitstreams contain CRC32 checks. If these fail, the FPGA won't be programmed. I've had similar problems when I started using FPGAs and it always turned out to be a constraint problem (assuming your board is build adhering to Xilinx's design guides). It is more likely that your contraints are wrong of absent. There is a way to check for unconstrained paths; use google groups to find past messages on that topic in this newgroup.

It is possible to make verification maps that skip memory elements (Xilinx has appnotes on that subject).

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Reply to
Nico Coesel

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