Hi, i am using the Spartan 3 (XC3S200) and the onboard clock on this FPGA works at 50Mhz, 20ns. Does anyone know how many instructions this FPGA can do in one cycle (20ns), in other words, what is the CPI(clocks per instruction) of the SPartan3.
I want to make a delay that lasts for 1 micro second by using an incrementing counter. If the CPI for example was one, then i would have to increment the counter 50 times to get a delay of 1 micro second.(1*us / 20ns)
Is that correct ????? thanks !!!
Spartan-3 isn't a processor so the clock used generally determines the maximum rate that things can change at. You can create another faster clock by multiplying the input clock, within the Spartan-3, using a DCM. You can also clock different resources on different edges of the clock.
There are lots of ways to do your counter either incrementing, decrementing or some other encode scheme but generally you will count 50 clocks of the 50 MHz to get 1uS.
John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.
An FPGA is not a processor. One way to look at it is that the XC3S300 can run up to one instruction every 10ms or so. But the instruction is about 1MBit in size and can do a lot of things simultaneously or sequentially. For example you could use a few hundred bits of that instruction to delay an input signal for exactly 50 clock cycles.
Or you can load a single large instruction (or configuration how FPGA people tend to call it) that processes smaller instructions compatible to some RISC CPU at a rate of a 100 MIPS or so.
Or you can do both at the same time.
Kolja Sulimma
snipped-for-privacy@gmail.com wrote:
Spartan3 is not a processor...
With Spartan3 (and with other FPGA) You can design Your processor or implement a processor disigned by someone but in each case the "CPI" depend on how You (or someone) implemented the processor !
You can not implement a processor at all but simply design something using sequential and combinatorial logic ("flip-flop", "and", "or", "not" etc)
Sandro
Kolja, I think you meant "one instruction every 10 nanosecods". This thread addresses users who really do not understand the parallel nature of FPGAs. So, powers of ten are important to get right... :-) Peter Alfke, Xilinx
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
Hi Peter,
no Kolja did mean 10ms !! per instruction of 1MBIT lenght ;) so in that context the magnitutude is correct, but I agree its not to be understood so easily.
1MBit instruction widht is not usualantti
Hi Antti, Im wondering if i had your point correct, do you mean a 1MBit instruction, 1MBit in width. If this is the case, how would you ever store that instruction?
I think Peter wouldnt like people to think that S3 are slow 100hz machines...
cheers
schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
It wasnt me, but Kolja who talked about the comparison of like: 1Mbit wide instruction executing at 10ms per intruction.
I think Kolja wanted to compare somewhat the FPGA versus processor (maybe not very succesfully explaining it) if I understood him correctly. This was far fethched comparison in any case.
Sure FPGA run WAY fast. but if you reconfigure the FPGA in loop within 10 ms loop period then the 'instruction width' is same as bitstream length? :)
maybe I cant explain it any better than the poster (Kolja) I did refer too, but I think I do understand kind of what he wanted to say. And in his context he did mean 10ms not 10ns.
Antti
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