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Spartan 3 configuration download error

Hi,

I am using the Xilinx ISEWebPack 8.1i together with a Spartan 3 Starter Kit (Digilent, bought from Xilinx). Now, from time to time I get an error message about failed program download to the FPGA from the Xilinx download tool.

The procedure I use for download is always the same: generate .bit file, Initialize chain (first select .bit for the Spartan, then bypass the PROM), then right click on the Spartan Icon, select "Program". Mostly then, "Success" is signaled, but, seemingly randomly, "Failed" is returned as a big red warning sign. In these cases I usually reset to the PROM-configuration and try the cycle beginning with Init-Chain above again, sometimes I shorten it to just doing the "Program" with right-click-select. After a couple of tries, this seemed to work at all times.

Now my question: What is the reason of these errors? Are they just random mishaps or can they be caused by errors in my design? Are especially timing errors in the design a possible source of download errors? (I ask this last question, because I have just completed a little state machine, that lets my processor interact with the SRAM as if it were synchronous. I used what I thought was a conservative and safe design with comfortable timing margins, but afterwards had two paths with 2.7ns "slack?" on a 10ns clock. As I inspected the paths in the post PAR timing analyzer, they seemed to me falsely analyzed and I decided to make a .bit file and download anyway. Superficially it seems to work (my cpu is correctly executing an endless loop writing to screen and copying memory blocks in the SRAM) but first I got repeatedly these "programming failed" messages, chance?).

Thanks in advance for all answers!

Jürgen

--
Jürgen Böhm                                            www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?"  R. Thom
Reply to
Jürgen Böhm
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Timing issues are not going to effect the ability to program. Timing issues will cause you to recieve values that you are not expecting inside the design.

Are you using the USB or Parrallel cable? A programming error occurs becuase the transmision to the FPGA is corrupted. You could have a bad board where the JTAG header isn't connected well. That would affect transmision and make it sparatic. You could have a faulty programming cable that could make it sparatic. Your USB or Parrallel ports could be sub standard and not sufficient to the task.

Try checking those areas. Timing in your desgin will not effect your ability to down load.

Reply to
Dwayne Dilbeck

Try to set the programming transfer speed to some lower values. This will fix problems with cables, PC parallel ports etc.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

I use the so called "Parallel Cable 3" (Digilent JTAG3) (connected to the so called J7 header of the Starter Kit). It can be found as JTAG3 cable on the page

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As it is advertised as a "low-cost-solution", one could speculate about the cable as the source of the problem - but maybe another reason is, that I left the cable plugged into the board for months and maybe somehow oxidation crept in.

Thanks for this information - it is always a bit difficult for an FPGA hobbyist without academic background in electrical engineering not to fall prey to vague ideas, speculations and misconceptions.

Jürgen

--
Jürgen Böhm                                            www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?"  R. Thom
Reply to
Jürgen Böhm

Reply to
Peter Alfke

My aoplogies. The point of my email was not to generate vague ideas, speculations and misconceptions. It was honestly meant as a brain storming tool to figure out what was wrong and inform you that the issue was not with the design process.

Aga>> Timing issues are not going to effect the ability to program. Timing

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Reply to
Dwayne Dilbeck

No, no, it came out quite right - with vague ideas, speculations and misconceptions I meant my mind-state before getting your (and the others) answer - now I see clearer at this point, thanks again to you and to the others who took the time to answer my question.

Jürgen

--
Jürgen Böhm                                            www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?"  R. Thom
Reply to
Jürgen Böhm

Try this: change the J8 configuration mode jumpers to "JTAG" ( off:on:off ) change the JP1 bitstream readback jumper setting to "disable"

see also these old posts & surrounding threads

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Brian

Reply to
Brian Davis

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