SPARC Based FPGA SoC system
I have always being amazed about the "art" of VHDL programming done by Gaisler Research, but the new release of GRLIB for LEON3 is even better.
GRLIB includes
- LEON3 (Sparc V8) Processor, cache, hardware mul/div, AMBA bus interface
- ROM/RAM Controller
- PC133 SDRAM Controller
- Floating Point unit
- AMBA Cores:
- Plug and Play AHB controller (peripheral module identify!)
- AHB/PHB Bridge (plug and play)
- AHB/APB reporting modules
- AHB PCI (master/target)
- PCI DMA Controller
- AHB adapter for opencores ehternet IP
- APB UART
- APB Timer
- APB GPIO
- Interrupt Controller
additionally are included several simulation cores and models.
GLIB is configured using flexible scripting system that supports "hw board support packages" that is the makefile can select what target hw board is used and configures all the toolchain for it.
makefiles can be used to start different simulators or generate bitstream using either xilinx or synplify synthesis.
There is no GUI builder (aka XPS in EDK) but when the bus modules are simply "wired" together in the toplevel module then all the bus arbitration is done automatically. So creating a customized SoC doesnt take more than few hours.
Of course available is full GNU compiler toolchain and scripts to compile example programs.
LEON3 can be used for uCLinux and Linux (demo images for both are available).
Debug unit allows full access to the AHB bus so it can read write to memory and peripherals. Special DSUMON application can be used to communicate with the debug module. DSUMON is also able to serve as GDB server so GDB debugger can be used as well.
Cycle accurate Instruction set simulator is available as well.
LEON3 SoC seems to use a bit more FPGA resources then as example MicroBlaze based system, I did an example SoC (with about the amount of peripherals)
MicroBlaze Soc: 1700 Slices Sparc SoC: 3500 Slices
What I would like to know is how much would the Sparc SoC decrease in resources if resynthesised using Synplicity Amplify, my bet is that it would come down to approx 2400 Slices from 3500
But even so, with XST synthesis its obvious that Sparc based SoC is already heavy competion to vendor SoC systems, specially when targetting the latest FPGA families and larger chips. In XC2V1000 the Small Sparc SoC takes around 50% (XST synthesis) what is relativly heavy price, but in larger family member and in case the peripheral IPs are large the actual percentage consumed by Sparc CPU comes smaller.
Of course I could imagine that its not so complicated to develop a Sparc-Lite version that could compete with resource useage with vendor CPU solutions.
Why I wrote this? Because I think that LEON3/GRLIB has had too few exposure, and well I always liked SPARC - it my personal favorite ISA. Once upon a time I wanted to obtain Sparc CPU chips made by Plessey, I had some idea for an commercial product - I never got them, by my idea still lives one, and now I can have the Sparc in low cost FPGA, thats great!
Antti Lukats