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[Sparan-II] Internal Power-On Reset Block?

Hi all,

we face a strange problem with our synchronized reset signal coming from the ISA-Bus. It seems that some part of the logic is not functioning correctly after reset-release. However I'am not shure.

I would like to implement a digital debounce logic for this reset signal, and for this reason I would like to have part of the logic on reset-ed ONCE after power-up and configuration. Is there a way to connect to this internal power-up reset signal, or shall I leave the reset connection of such a debounce block always negated by connecting it to permanent '0', for a active '1' reset?

Best Regards Markus

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Markus Meng
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Markus Meng schrieb:

Coming One Step further, we now have the following situation. The very similar Spartan-II design is working perfectly in a clean 3.3Volt ISA bus environment. Several thousand test runs using the the synchronized Reset logic never produces an error. The card is working as expected.

The very same card in a 'old' fashioned 5V ISA-Bus System with some overshoot on the signals crashes from time to time after RESET. Once this crash occurs, there is NO-WAY to reset the FPGA again. It remains "kind-of-dead". Only Power-Off and Power-On again can 'solve' this deadlock situation...

The configuration is loaded from an external prom only once after power-up. The ISA-Bus reset does not reload the bitstream but resets the internal FF to their initial state ...

Has somebody also seen this kind of strange behavior, where the FPGA can not be reseted anymore by subsequent resets. It remains in this state until power-off.

Is this a 5Volt compatibility issue of Spartan-II?

Best Regards Markus

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Reply to
Markus Meng

Markus Meng schrieb:

Hi all,

completing this what I started. It has NOT been a Spartan-II IO issue concerning the 5 Volt compatibility issue of Spartan-II. Spartan-II works perfect in our legacy ISA Bus environment.

Just in case, this comes up at another place

Have a nice Day Markus

Reply to
Markus Meng

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