Hi,
I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should be captured an put into a blockram. The OFFSET IN constraint, which I want to meet, says, that the DATA should be available 0.97ns before the CLOCK.
So far I have the data-lines into their IBUFDS (8 times) and into the data-input of the BRAM. Clock goes into a IBUFGDS, into the DCM, into a BUFG and into the clock of the BRAM. DCM_FEEDBACK is fed from the BUFG as well.
I have learned that from "UG331", the "Spartan-3 User Guide".1] So I set the DCM to "SOURCE_SYNCHRONOUS" and the phase shift to 0, for testing. I get in the Timing Analysis:
Slack: -2.134ns = 0.97ns setup - (4.5ns datapath - 1.4 ns clockpath)
So i set the PS to 120, just for curiousity:
Exactly the same results. The phaseshifting is accounted, in the DATASHEET the internal clock (which is correctly infered from the external clock on the input of the DCM) is displayed with a phase from
1.875ns, but this is not reflected in the constraints. Am I missing something?Thanks a lot, Christian
1] It says there: "The SOURCE_SYNCHRONOUS setting essentially zeros out any phase difference between the incoming clock and the deskewed output clock from the DCM. The FPGA application must then adjust the clock timing using either the Fixed or Dynamic Fine Phase Shift mode."