Does anybody know how to do source-synchronous I/O constraints in Synplify? (That get forwarded to the Xilinx backend tools).
I hit the problem every so often where I have a reference clock coming in on a pin, and that clock is used to clock a source synchronous interface where the clock is forwarded.
The output constraints all relate the output data bits (at the pin) to the input reference clock (at the pin). An ideal situation would be to be able to constrain the output data relative to the forwarded clock, but I'd settle for just being able to nuke the I/O constraints relating the data outputs to the reference clock.
Thanks, Jeremy