Hi all,
I am exploring the possibility of using a FIFO between the OPB and my custom IP-core. I want to write data from my IP into the FIFO. I see that the FIFO has an output called RFIFO2IP_WrAck. This is an ackonowledge signal that the fifo asserts when it is ready to read data. According to some examples it seems like this signal can go low randomly, that means regardless of the fifo being full or not. To me this means that the data I want to write to the fifo must be buffered before it enters the fifo, resulting in 2 levels fifos. Then it is better to use a self written FIFO that can accept data all the time(unless when the fifo is full, of course).
Is my assumptions wrong ? In real life, maybe this signal never goes low ?