some virtexII clock pads are useless??

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For test my fpga clock, I input a clock throuth one of the dedicated
clock pad, and output it from a general I/O. From the oscillograph, I
found some clock pads can give the correct signal, and the same clock
input the other clock pads only have the '1' output.

p.s. I use the same vhdl code as follows: clkin-->ibufg-->clkout.
Just differences in assign clock pins.

Any comments would be appreciated! thank you in advance!


Re: some virtexII clock pads are useless??
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Here's a suggestion, in the V2 datasheet it says that "As long as the
presently selected clock is High, any level change of S has no effect .". Is
that your problem?
Cheers, Syms.



Re: some virtexII clock pads are useless??
No, Symon.

I am afraid not, my problem is a real problem. It's something very simple
and fundamental.
I am switching between the two clocks when I loop one data path to another.

But thanks, appreciate it. Can you think of anything else?

Vladislav.


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