Hi, I am simulating a Xilinx Design which uses all of the 8 Rocket IOs present in the V2P7. All the Rocket IOs are identical except for their Differential Data Inputs. I use the Transceivers as Receivers only and am using the Gigabit Ethernet mode with 2 byte path. The problem is that out of the 8 channels I have, 5 of them see the idle (D16.2/K28.5) correctly and accordingly align the data at the right boundary. The other three channels don't seem to work. The output from them is XXXX. Also another thing i noticed is that if i introduce a slight delay into the refclk input, the behaviour of the 5 previously Ok channels also changes. Instead of seeing a 50BC(D16.2/K28.5), they seem to lock on K28.5/D16.2(BC50) and thus the data gets misaligned (a
1 byte shift in the data out from the Transceivers). I am implementing the clock scheme as suggested in the Rocket IO transceiver user guide for the two byte path. Could this be a timing issue with the RefClk ? What about the XXXXs ? I will greatly appreciate any suggestions with regards to this. Anyone who has successfully simulated and used these Transceivers, could be of great help. PLEASE HELP ! Thanks a lot, Adarsh- posted
20 years ago