Some FPGA questions

A few links that might be of interest to you (this is Xilinx/VirtexII slanted):

Read this first:

You need to read through the VirtexII data sheet:

and user guide:

Then move on to the development system manuals:

probably get started with this one:

In the begining it probably doesn't make any difference which language you go with. In fact, Verilog might be faster and quicker to learn, since you know C. You'll slip right into it. However, if you want to go beyond canned push-button designs in FPGA's I think it's fair to say that nothing beats the capabilities afforded by VHDL. This is almost the sort of thing that has to burn you for you to "see the light" and understand why on tool can be (and is) better than the other.

For the record. I use Verilog.

For the record #2. I know that I'll have to migrate to VHDL because Verilog has already gotten in the way of optimizing my designs.

Download Xilinx Webpack

Avnet and Insight/Memec have nice boards. The range is from about US$200 to over US$700. The Microblaze board (expensive) might be what you are looking for.

Once you understand the game, and if they are well written, yes.

The toughest thing to understand for a (let's generalize) software guy is that, in the FPGA game, perfectly good code does not equate to a working design. You can have an HDL module that is a thing of beauty and does exactly what it is supposed to do in a logical sense. However, to make that chunk-o-code work in a chip there are a number of other considerations that come into play. So, yet, generally speaking you might be able to use downloaded code, but, in the context of a non-trivial design having good code alone doesn't do the deed.

I think so. Hey, no delivery schedules! That's paradise!

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian

To send private email:

Mike,

Another link which might give you a good starting point for writing CPU cores in Verilog/VHDL

I also agree that the xilinx web pack is a good place to start, you get Modelsim and other goodies.

This is because languages like VHDL are HARDWARE description languages, you code should be written is such a way that a synthesis tool can recognise it as a counter, memory, mux etc. The tool will then have a better chance at optimise your design.

A bit of hardware design experience doesn't go amiss either, it is sometimes a good idea to think about how the problem could be tackled using descrete logic blocks and then convert them into components.

Matt

VHDL.

Verilog

to

looking

that

that

A good start here would be to look at Xilinx's Picoblaze. It's a very simple CPU core that's freely available.

If you look on the downloads page of my web site you'll find a tutorial which walks you through building a design based on the Picoblaze with Xilinx's free tools, Webpack.

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

If he knows and prefers ADA, (presumably for its unambiguity, clarity and precision, compared to C) he will prefer VHDL, for precisely the same reasons, to Verilog.

If you prefer Verilog, you probably prefer C to ADA. They are certainly more concise. But that comes at a cost. (I don't mind a bit of extra typing - in both senses - to save scratching my head)

Consider also

If you have 74 series experience, you'll probably be fine. The limitations are along the lines of keeping the design realisable in hardware, such as avoiding code that would try to synthesise to a flipflop with two clock signals, or compare a logic level against "Z" (high-Z) instead of '0' or '1'.

Such non-realizable code is of course perfectly OK in a testbench, but not in the design itself! Download and read a guide to VHDL coding for synthesis - Xilinx have a good one - and it makes pretty good sense.

- Brian

completely

All suggested Xilinx tools. However, Altera Quartus, the free web edition, also supports VHDL (now) and you can do the simulation after routing (a little bit different than VHDL simulation).

would

environment,

You can find a long list of boards at

standard

Alter Nios 32-bit RISC or my Java processor are about 2000 LE (logic elements). A LE is usually a flip-flop with a 4 bit LUT. Estimating gate count in FPGAs is problematic. The mentioned 2000 LEs are about

Martin

---------------------------------------------- JOP - a Java Processor core for FPGAs:

That gives you a leg up. VHDL is based on Ada.

History. ASICs and Verilog were first.

Consider waiting on picking a board until you've learned the following using google, a text editor, sim and synth tools:

1. Synchronous Design Techniques
2. VHDL language and testbench design.
3. VHDL subset for synchronous design.

Free IP is not always well written or well documented. Once you know how to design synth code, writing your own may be faster than learning and fixing the "free" code.

Yes, this is a common hobby project. Most VHDL texts have an example. But consider that FPGAs are often designed in to do jobs that CPUs can't handle efficiently.

-- Mike Treseler

I'd like to thank everybody who answered my questions. Very helpful group here! I've downloaded some tools and ordered some books, and I'll just hope not to disturb the horses.

BTW, is there some convenient list "ranking" the various FPGA families available, in terms of size (however that might be measured), and cost?

Also, where do CPLDs end and FPGAs begin? Is there some fundamental difference in architecture that draws the line, or is it just a size thing, or??? Are all CPLDs smaller than all FPGAs? (again, however that might be measured)

Thanks again,

Mike

you

I wasn't refering to synthesis or inference with the above statement. A design within an FPGA is a combination of sound logic (the "program" does what it is supposed to), correct inferred synthesizable logic, explicitly instantiated structures, timing specifications, routing and placement.

Generally speaking, standard portable HDL might cover the logic and inference part. I said "might" because you might have to prod it this or that way in order to get 100% inference to your satisfaction. The minute you start to explicitly instantiate primitives you are no longer portable (meaning across device/vendor boundaries). But, now you have the logic you wanted, and, all of this can live within HDL files. But your design might not work.

Example: A pipelined adder feeding a multiplier. The HDL is simple. Now, let's say you want it to run at 180MHz. This is a case of "perfectly good code does not equate to a working design" as I said. In order to achieve this level of performance you have to resort to a whole host of timing specification as well as strict floorplanning. The PERIOD constraint is not good enough. You need to use specific connectivity from switch boxes into and out of the mulipliers (about 560ps delay), for example.

The HDL description might be perfectly sound ...

(descriptively) first clock add a to b produce c second clock add c to d produce e third clock add e to f produce g fourth clock multiply g by h produce result.

... but, despite the code being "perfectly good" this alone won't work. In the sofware world the only parallel I can draw is perhaps with code that might try to access a resource before it is ready. Even though the access logic and algorithm might be perfect, the time factor (or readiness factor) still has to be a part of the whole package.

Howdy Mike,

Unfortunately, as broad as your question is, I don't really have a choice but to answer it in a broad way: part numbers with big numbers printed on them tend to cost more than the ones with small numbers... seriously! Prices range from under $10 to over $1k. Prices on these parts are just like any other mass produced IC... they are volume driven. Just look at the useless prices that the silly Xilinx product managers put in their press releases.

The only thing that is a little strange is that only the very newest products cost a lot. The parts that were introduced a year or so ago tend to be less expensive (and much better supported) than parts from three or four years ago. Not to mention the newer parts have considerably more features and resources per dollar spent.

Definitely go with the newest generation you can afford.

Lastly, some vendors have a line of high (performance/feature/resource) parts and a line with not-quite-so-high (performance/feature/resource). Unless you're doing something pretty crazy, you probably don't need the high line. As an example, earlier this year, I designed a 12 port Ethernet packet manager, complete with overflow handling, in a Xilinx Spartan IIE (XC2S150E) [that's on the not-quite-so-high line of products]. It runs at 100 MHz and handles over 700 Mbps per second in each direction.

At the opposite end of the spectrum, I have a co-worker that is currently implementing some logic that brings in data at 2.488 Gbps and processes it at 311 MHz. He's using a Virtex-2Pro [one of the high performance parts], mainly because the Spartan line won't handle the 311 MHz clock rate.

As you appear to have surmised, there are some very high end CPLDs that would, in some cases, do more than low-end FPGA's. In almost-too-general-to-be-useful terms, CPLD's tend to be designed for wide input functions and relatively low propagation (and easy to predict) delays. Most (all?) modern FPGA's are build on sea of four-input lookup tables. Lookup tables can be cascaded (where the variability compared to CPLD's comes in) to create huge functions. People may find exception to some of these statements, it is the general concept that I'm trying to get across.

We've found that FPGA's can be used to do most things that CPLD's do [except FPGAs must be programmed upon power-up], but not the reverse.

Have fun,

Marc

From read "This is because languages like VHDL are HARDWARE description languages, you code should be written is such a way that a synthesis tool can recognise it as a counter, memory, mux etc."

which is something that I read on this group when I started out, but didn't really appreciate how important this fact is. So I got advice about which book to learn VHDL from and I bought The Student's Guide to VHDL by Ashenden, starting reading it alongside Digital Systems Design Using VHDL by Roth and all along I had the feeling that there was something wrong with the way both books were teaching the subject, and recently I found out what it is and it is that the Ashenden book just teaches the VHDL language from a theoretical basis, which means that it is good as a reference book to learn the language but if you want to synthesize your VHDL code to make something that actually works then this book (and the book by Roth) doesn't teach you how to do it.

So what I'd suggest is to buy one or two books that concentrate on the synthesis side of things so that you learn what code will synthesize to what hardware right from the start rather than just reading about the VHDL language.

After doing a bit of research into what books have been recommended on here and on amazon.com I bought the following books:

VHDL for Programmable Logic, by Kevin Skahill -

The first one has been mentioned on here favourably a few times and gets good reviews on amazon and from what I've read of it so far it is very well written and it is answering the questions that have been left unanswered for me when reading the other books. It's pretty basic, but that's exactly what you need when you're just starting out and I certainly wish I'd have started reading this book first.

The other books is a bit more advanced and I've not started reading it yet because I'm going to read it straight after the book by Skahill but it gives you a load of VHDL code for real cicruits and explains the code and what hardware the synthesizer produces. I can't tell you whether it is badly written yet (one of the people who've reviewed it on amazon said it's badly written) but from flicking through it it looks at just the right level for when I'll have finished reading the book by Skahill.

As others have said, there's masses of free literature on the Xilinx website as well.

Thats right for a specific kind of problem. A fpga with 1000 logicgates could be seen as a box with 1000 NAND2s you could do nearly any logic. A CPLD would offer you (fictive example) a the same time a box with 200 Nands followed by 50

Neither fusebased FPGAs nor Fpgas with flashram need to be programmed during power-up. I think there is nothing a CPLD could do that a FPGA can't but sometimes a CPLD is cheaper or needs less power or area.

bye Thomas

Thanks a bunch for your comments and the book suggestions. What you describe certainly makes sense, and it sounds like a pitfall that I would have gone into head first. Now, having been warned, maybe I can get by with just a scraped knee or so!

Mike