Hi Antti,
At ALSE, we design all kinds and brands of FPGAs and have been doing so for years and years (the first FPGA I dealt with was a XC2000 under XDE,- 17? years ago-). Until less than two years ago, we did design more Xilinx than Altera parts (we respect the customer's decision when he wants a particular device or family). And ISE is based on a technology (Synario & ECS) that I supported even before it had a name -and I more than liked this tool, still use it occasionnally-. When Quartus was launched, it was terrible, and stayed that way for a while. However...
IMO and backed up by concrete experience, I would say that the progress made by Altera with Quartus tools (and devices) over the last two years has been tremendous and probably gone very much unnoticed, until recently.
Quartus II has progressed a lot, and it's not over... The new device architectures (like MaxII) are as surprising as they prove efficient concretely. We love the Cyclone family : cheap, extremely low power and they are usually faster than the usual applications require even in their lowest speed grades.
- As of tool quality, I keep my fingers crossed, but I don't fear loading the latest QII release (even beta) and start using it right away in the middle of challenging designs. I usually let other tools "ripe" a bit.
- As of integrated synthesis, both for QOR and language coverage (VHDL) I won't comment, by fear of offending third party tools vendors. I've witnessed 30% smaller designs with QII v4.2 as compared with older versions, and I have problem with standard descriptions with XST which are perfectly supported by QII now. There are still a few things I would like to see added in QII (like character'pos), but they should be in 5.0 or 5.1 and I stopped asking for VHDL QOR improvement.
- QII's Static Timing Analysis + constraint-driven P&R + Physical synthesis are impressive. Most FPGA users need to be educated in order to take advantage of it. Physical synthesis can for example fix design errors by automatically compensating data or clock delays, it can precisely adjust delays for SDRam interfaces, etc... I'm not saying other tools don't have this technology, just that users are often unaware that it's in Quartus II.
- Tcl/Tk and command-line tools are so easy to use ! (you find a Tcl console in almost all tools now -yes: ModelSim too : just type parray env-). You can build and download an FPGA with a single double click on a batch file and never see the GUI if you want to, with a trivial script. This contributes greatly to the ease of use of our Tornado FPGA Board and Tornado Education Kit.
- SoPC is probably the strongest advantage I see as of now for Altera. The NIOS II processor, the Avalon switch fabric, and the Tools around them have proved their value. I know several companies even purchased the NIOS license... for ASICs.
- RTL and Technology graphical Views are very decent, and the cross-probings between all the different descriptions is handy when investigating.
- The Constraints Editor, initially clumsy, is now very powerful & versatile. You can for example easily import export CSV pin assignments (with PCB tools or Excell). It is well organized and easy to use.
- The GUI commands have their immediately visible Tcl counterpart, so it's a trivial task to automate even the most complex settings. When we deliver an FPGA design to a customer, we only have HDL source files and a single "does-it-all" Tcl script (which also includes the pin & other assignments).
- SignalTap and InSystem Memory Contents Editors are _VERY_ easy to use (and cheap if not free).
- LogicLock makes floorplanning (almost) easy when the need comes.
- JTag (Jam) player is nice in some cases. Not sure Xilinx has the equivalent public code. (well probably)
- I think the cost is lower for the full version of QII compared with Foundation and equivalent options (ChipscopePro) but prices move often.
- It's very easy to integrate other tools within QII, or to integrate QII inside other tools. I don't think any other tool is as open as QII.
- OpenCore IP protection scheme is clever. It lets you play with IPs as you please. The megawizzard is also easy to use.
- Power estimation in 4.2 is now simple to use, both as an early tool, then along when the design gets refined.
- Early estimators, and fast assignment verifiers, Design assistant, Performance advisors definitely make the designer's life easier.
- Never used DSE nor distributed computing (hope I won't have to), but I know it's there.
- More new features are announced.
As far as I know, Altera bought a couple of small but very brilliant companies that are behind these technology leaps.
On the minus side for Altera I would mention :
- Truly incremental P&R is coming, but still not quite here yet. Many users are impatient (it will be welcome for the big chips).
- For simple designs : Analysis & Elaboration must be run in order to view the hierarchical dependencies (ISE does this automatically), not a real issue but it's a bit unexpected for ISE users when they try QII. For big designs, you don't let the tool guess what it should compile and in which order; we use scripts.
It's very easy to use Quartus II and simply not unleash its power even when you need it. That's why we made efforts to build and offer (with lots of help from Altera) an extensive 2-days Training course in France, and we get an excellent feedback on it.
What we try to say to our customers is that Quartus II now deserves spending some time learning its many features and capabilities. For simple things, not much if anything at all is necessary (a batch file can do everything), but challenging tasks will be much simpler with a good understanding of the engine under the hood.
--
As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback & experience to
share ?
Obviously, we don't fear designing Xilinx chips (we design mostly very complex
applications now) and ISE is easy to use. Besides the lack -as far as I know- of
easy
and well documented scripting (Tcl/tk), my worst grief is that it's way too easy
to
have the focus on the wrong design entity :-) This feature didn't exist in
Synario,
and it was much less error-prone. Definitely minor, but irritating. With QII,
you can
change your focal point, but you can't do it without noticing.
VHDL synthesis (XST) has also some issues and weaknesses, and I sometimes have
to
partially rewrite some of our IPs for this reason (I complained a couple of
times
about poor support for qualified expressions for example).
I find Impact's look and use a bit clumsy and old-looking, but it works. I guess
it
has been improved in 7.1.
I also hope they removed or rewrote these offending VHDL "examples" !!! (like
j2c_vhd
on top of my head).
On the X. side, I found Xilinx Tech Support outstanding (maybe only ModelSim's
does
impress me even more).
I loved ECS in Synario and first ISE versions, with the generic symbol library
and
all the cool utilities related with HDL, but I don't like what it became in the
latest versions of ISE. But schematic editors are usually a matter of personal
taste
(I'm not a huge fan of QII's schematic editor either) and we don't use them much
if
at all (top levels only, if we find enough motivation).
If you plan to stay with Xilinx, don't start using Quartus ;-)
Things are very cyclic in this industry, so I expect an effort from the
competition
to regain the lost terrain. It makes things interesting for us to watch. The
good
news are that the end-user is usually the winner on the end, with powerful and
affordable tools and devices. But high-end FPGAs and applications are bringing
us
lots of challenges : high level descriptions and modelling, ABV, high-speed
design,
power issues, P&R challenges, IPs reuse, collaborative design... we'll see.
Bert Cuzeau
--- The opinions above are my own only.
--- I may be wrong on some issues.
--- If you think so, or believe I am unfair in any way, let me know.
Antti Lukats wrote:
> Hi
>
> first - I am a very Xilinx biased (possible because I have way more Xilinx
> boards)
> but the latest Quartus seems really easy and in some cases better than X
> tools
> (at least the built in programmer is FASTER to use than impact)
>
> Story:
> After getting a nice application tested on Xilinx FPGA I just out of
> curiosity
> tried to port to Altera devices, the only problem I had was related to lack
> of documentation on the cyclone_jtag and maxii_jtag, after solving those
> the original xilinx code compiled without changes and worked too :)
>
> http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter
>
> after first success with Cyclone, I tried it on MAX2 and worked again :)
>
> MAX2 is really nice well its not so much an PLD but more like
> Xilinx XC2K reinvented and made flash based ;) anyway it is
> really a heavy player on the flash device arena as the other
> suppliers Atmel and Lattice are not yet shipping their low-cost
> flash FPGAs
>
> Antti
>
>
>
>