Software instabilities with EDK 10.01 and PPC405?!??!!!

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Hi folks,

I am short before going mad...

I have a Xilinx ML403 board with a Virtex 4 FX12 FPGA sitting on my desk.

I use an EDK generated PPC405 design as a submodule.

My current task is to interface with a simple IIC chip via the Xilinx
IIC core. That works - from time to time.
My software behaves completely strange - hangs, seems to skip parts,
runs into Xilinx' assertion stop code, etc...

I use the following libs and drivers:
Xilinx intc, iic, uartlite, xil_printf
libc's printf

I tried to dig into the problem using the Xilinx supplied XMD debugger.
It looks like I am suffering from "side effects": I have seen data going
corrupt (function pointers NULLing) while execution is somewhere else.
I have also seen program exception and machine check exeptions in the
PPC's ESR register :-(
Behavior changes with position of code in memory. Sometimes an inserted
or removed operation completely changes the behaviour...

So the question is: Does anyone have similar experiences? Is there any
known corrupt driver code in the last EDK revision?
Am I doing something badly wrong?

If you have some ideas, PLEASE let me know... I can provide more details
on request.


Thanks a lot,

Philipp :-)




--
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Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
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My guess would be that you have a timing error.  Does your design meet
timing?  Do you have a timing specification?

Are you running from external memory?  Can you run a memory test on
it?

Alan Nishioka

Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
Hi,

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That *could* be.
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I have to dig into that on Monday....

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Nope. I am using the EDK generated .ngc netlists and the EDK generated
.ucf file.
My design (it's connected via external memory controller) doesn't have
critical timing and the synthesis estimate says 140Mhz.... So I didn't
care for timing...

But what could I do if the EDK design does not meet timing specs?

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Yes. DDR

Hm... I have tried the memory test demo application once. Perhaps I have
to try it again....

Best regards,

Philipp :-)

Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
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Hello Philipp,

Are you using an operating system, or are you running stand alone
code?

Your symptoms sound like they could be caused by a stack that is not
big enough.  If you are using an OS that supports virtual memory, the
stack and heap sizes for each process are dealt with for you
automatically.  If not, than you need to pay some attention to make
sure that their default values will work for your program.

printf can take a lot of memory resources, and every time you move
printfs around to try and debug, the symptoms can change.

If you are running stand alone code, check what the stack and heap
sizes are set to in EDK. In the Applications tab in the Project
Information Area window, select your program, right click, then select
Generate Linker Script.  That will pop up a window that list the stack
and heap sizes and other stuff.  The default is 0x400 bytes, or 1k
byte. That is big enough for our boot loader that loads Linux from a
MiniSD card, and does some stuff with SPI roms. It uses xil_printf,
but not libc printf.

Try increasing the stack and or heap sizes and see if that makes a
difference.c

Regards,

John McCaskill
www.FasterTechnology.com/products.html

Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
Hello John,

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I am running standalone code. I am using the Xilinx supplied driver
framework to get the CPU up and running etc.

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No, currently no OS :-)

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That's an important hint!

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I just tried it - it MAKES a difference!
But how can I determine the correct stack size? Stopping the program in
the "deepest point", look at the stack pointer, add something for
interrupt purposes and use that "counted" value?
Which of my data goes to the heap? I don't use dynamic memory allocation
(btw do the libxil and friends support a working malloc(), free() etc.?).

Many thanks for your tip :-)

There is a new EDK problem: I tried to change the PPC cpu speed by
changing the cpu clock output frequency of the EDK clock generator. Did
that via GUI and by editing MHS file. I can do a "make netlist" without
any problems. But then, later, PAR gives me an error mentioning a
dcm...clk..something<7> signal that has a constraint but doesn't exist.
I tried to find the constraint but I don't know where to look. I also
grep'ed through the EDK generated netlists (after running ngc2edif) and
did not find that signal. And I don't have a clue where I even could
have a constraint file mentioning that signal....


Best wishes,
Philipp :-)

Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
Problem solved!

Ist was really a stack/heap insufficiency combined with a very little
programming error (Forgot a wait condition related to the Xilinx IIC
driver) that caused my design go mad.
Now everything seems to be fine.

Thanks again,

Philipp :-)

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