Software Defined Radio auf Xilinx Virtex 4

Ich k=F6nnte mir aus diesen Angaben auch keinen Reim machen. Sollte Anderen das Board und verwendete hdl-Funktionsger=FCste bekannt sein?

Auf englisch oder in besserem Deutsch fragen stellen, Weiterarbeiten, Konkrete Fragen ohne konjunktiv stellen, relevantere Informationen zu den Fragen liefern.

Chindgi,

I apologize for not replying in German, my written German is worse than my spoken German, which is only at grammer school level.

It seems like you have the conversion of the analog sine wave to digital (AD), and conversion back again (DA) working in both VHDL, and hardware, yet you say you can not see anything on the oscilloscope.

First, did you simulate the design? Does the simulation test bench work?

Second, are you able to input, and output static (unchanging) DC voltages? This would be my first test, before I tried AC (sine waves).

If this is an issue with clocking (sampling), the DC will work, and then the AC will have issues with frequency response (just guessing).

If the DC does not work, then I would use a logic analyzer (if it is Xilinx, Chipscope(tm) is soft IP that may be part of your design, and allows you to probe your digital signals inside the FPGA and see if they are what you expect in the DC case).

Perhaps a German speaker will be more helpful to reply,

Austin

Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal die "lingua franca" dieser Industrie und Technologie.

Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen zusammensetzst, um mit Deinem Projekt voranzukommen. Viel Erfolg ! Peter Alfke, Xilinx Applications Engineering

If he's more comfortable with German then let him write in German, whether or not it's his native language. Of course, there may be, as you say, few who understand him and can reply. I know almost no German, but that's my loss as much as his.

If I see here a language I don't understand, I just ignore it.

If this is a "single-language" group, I'm in the worng place. I don't do segregation.

Mike

Nach zwanzig Jahren haben wir nicht entschieden, welche HDL-Sprache das "lingua franca" ist. Der Babel-Turm ist nicht zu vermeiden. Solange wir mehrere HDL-Sprachen verwenden, gibt's keinen Grund warum wir nicht mehrere menschliche Sprachen verwenden sollen!

Vielleicht koennten wir nun entscheiden: zum menschliche Sprache, English, und zum HDL-Sprache, SystemVerilog. Hat jemand was dagegen?

-Kevin, Xilinx

Can't possibly be a single language board, we let VHDL, and Verilog users both post here. :-)

I appreciate the variety of both HDLs and human languages. While a VHDL to Verilog translator typically runs thousands of US$, a free website I use for the other language issues

translate.google.com

is very helpful.

It seems the original post has to do with troubleshooting a design in a real system. There isn't much to suggest here since there is so much that *can* go wrong. Only by applying debug techniques with controllability and observability at appropriate points to effectively partition the design can the trouble be found. Coding problems might be obvious to the casual (trained) observer, but "it's broke" often gets us nowhere.

I can suggest using test points at various points through the design - perhaps even ChipScope - to figure out if everything is progressing as expected until something breaks.

Gesundheit,

- John_H

If the converters are AC coupled, DC won't get through them. I prefer testing with AC for that reason. He can perhaps put a signal generator in the FPGA (a CORDIC will work nicely) to drive the DAC to get the output side tested.

Make sure the clocks and any data enables are getting through to the converters. Also, make sure that any set-up to the converters has been done properly (many use a serial interface to set up parameters, and won't operate until you've programmed something into them).

Unfortunately, I've never learned any German, so I'll have to count on someone else to translate this for Chindqi.

aust> Chindgi,

messen .

Vermutlich hast Du einen ganz banalen Fehler in Deinen VHDL Quellen. Am besten trennst Du die Aufgabe in ihre Bestandteile auf und betrachtest jeden Teil fuer sich.

Das ADC-Interface kannst Du beispielsweise testen, indem Du die eingelesenen Daten ueber eine digitale Schnittstelle ausgibst (zB ueber RS232). Das DAC Interface in aehnlicher Weise, indem Du Daten digital eingibst und mit dem Oszi schaust was rauskommt.

Sobald alles fuer sich alleine funktioniert, kannst Du die Teile zusammenfuegen.

Viel Erfolg, Marc