Hi, when I synthesize the following, I get warnings.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce is generic(N : integer := 20); port( clk,reset : in std_logic; button : in std_logic; debounced : out std_logic ); end debounce;
architecture Behavioral of debounce is type state_type is (s0,s1); signal state_reg,state_next : state_type; signal cnt_reg,cnt_next : unsigned(N-1 downto 0); begin process(clk,reset) begin if reset='1' then state_reg