Small FPGA

"Sylvain Munaut" schrieb im Newsbeitrag news:42c25994$0$28322$ snipped-for-privacy@news.skynet.be...

there unfortunatly arent any FPGAs in VQ44 or VQ64 package :( the smalles FPGA packages (non BGA) are TQFP100 what is pretty much larger already. by had you can actually solder very nicely also QFN packages but there are virtually no FPGA in QFN at all,

actel A3P030 should be offered in QN132 (I assume its QFN not BGA!), but ASFAIK it is not available

Atmels FPSLIC is coming to small 8by8 package, but again its not available and I think its BGA (there is not even info about this)

so everything that has smaller PCB footprint than TQFP100 is already in BGA or not available

you should try to fit your design into PLD, you have better luck to find smaller PLD devices, but well sure the PLD prices go up much more faster when you need more macrocells.

the 'design for fit' for PLDs s totally different from FPGA, so by doing special optimization for PLD you may fit way more into a PLD then you think

two examples from my experience

1) a complete MMC card controller that support MMC protocol (not SPI) and loads the all bits from MMC card, it takes 20 PLD macrocells (in coolrunner, 21 in XC9500), that is way less than, well if you think its only 20 flip flops! this design is specilla optimized for PLD

2) recently I was asked to display a textual message on intelligent display, using a PLD, well the PLD was already full having a macrocells free, but to my own surprise the display of an text string involved only an addition of 1 flip flop, well this one flip re-targetted most of the existing macrocells to have secondary function...

counters and muxes and registers are quite easy in PLD, but the amount of registers is sure limited, all flip flops have a way higher 'price' than the flipp flops in FPGA

hm, the larger PLD are also in packages larger than VQ64 :( so there isnt much that fits your requirements

I would go with MAX2 in TQFP100, but if that package is too large than you have to wait for APA030 QN132, or maybe there is something else coming out sooner, lattice promised some new PLD devices to be announced 'after your summer vaccation'

Antti

Hi Antti

Yes, indeed my "style" is more based on FPGA experience. What would be the "CPLD" way to code a debouncer ?

I'm kind of in a hurry ;)

Thanks for the insight,

Sylvain

"Sylvain Munaut" schrieb im Newsbeitrag news:42c27017$0$23344$ snipped-for-privacy@news.skynet.be...

think

not everything can be pld optimized. if you only have 100mhz clock and need some low frequency then you need some amount of flip flops to implement the counter.

so if you need to debounce a mechanical switch you might need lots of flip flops (assuming only high frequency clock is available) - a 'saving' in PLD would be to have separate RC oscillator to get low frequency needed for debounce

the most savings in PLD come from resources sharing, as example if you have a need a counter and and shift register, but they are never active at same time, you can use the same macrocells, that is 8 bit counter and 8 bit shift register consumes 8 PLD macrocells (but they are not useable at the same time).

the 500LE (if that is LE as in Altera) would defenetly fit into a PLD but the LE to PLD macrocell ratio depends on the application, if there is really lots of (wide) logic, 500LEs could be even as small as 72 PLD macrocells (eg fit XC9572 VQ64), if the design is register rich then the ratio would be 1:1

note that altera MAX2 is not a PLD, but simplified FPGA, so the LE to MAX2 cell is 1:1 there is no reduction

out

your

if in hurry then you must either use TQFP100 package or BGA

Antti

Hi Antti,

Finally I think I wont use PLD at all. A RC filter for "quick & dirty" pre-debounce and a simple 8bit µC to handle to rest of the logic will do. It doesn't need to be very fast anyway.

Sylvain

"Sylvain Munaut" schrieb im Newsbeitrag news:42c27a2c$0$29635$ snipped-for-privacy@news.skynet.be...

HAHA, that is good optimization!!!! from 500LE down to 0! with proper firmware you may not need the external debounce but it all depends sometime the rc network is good choice

sure if there is no direct need for high speed logic then small flash micro is better choice.

my current favorite is ATmega8 in QFN32 package, but thats all a matter of taste

Antti

"Sylvain Munaut" schrieb im Newsbeitrag news:42c27017$0$23344$ snipped-for-privacy@news.skynet.be...

A counter and some logic will do. CPLD or FPGA doesnt matter here.

Regarads Falk

The problem is that I need 8 of them + some other stuff, the debouncers fits but uses most of the 72 macrocells and the price goes high quickly for more macrocells.

Sylvain

"Sylvain Munaut" schrieb im Newsbeitrag news:42c2cdce$0$337$ snipped-for-privacy@news.skynet.be...

I assume the debouncers are for push buttons? This can be easyly handled in a microcontroller. And this is also very cheap.

Regards Falk

Then use less :) A debounce really just needs to remove the unwanted edges, so you do not need many macrocells/key. ie Slower clock, and fewer MC is another way.

-jg

If you need to debounce 8 switches, you might want to use a common anti-bounce delay cicuit. Accept any activation of any key, but immediately start a delay circuit that ignores all key level changes. That should suppress the bounce. Peter Alfke

Actel has the A1010B in CQ84. I don't think there are smaller packages left on market. Backdraw is the high price, and the fpga is only one time programmable. The fpga needs also 5V. And 500LE migth be far more logic than the a1020 provides. If you come to numbers >1000 you could Ask actel for the a54sx in the same package. The A54Sx come along with 3.3V. If your requirement small is only because of hand soldering, you could also look at other packages with 0.5 pin pitch like PQ and TQ.

bye thomas

Why not a small microcontroller like a PIC 10F series?

Here is a neat debouncer for the Atmega's (It does 8 keys at a time , PORTD in this example) written for AVR-GCC / WinAVR

Rgds Carsten

/**************************************************************************** Title: Debouncing 8 Keys Author: Peter Fleury

based on algorithm of Peter Dannegger Date: December 2003 Software: AVR-GCC 3.3 Hardware: AT90S8515 at 4 Mhz, STK200 compatible starter kit

Description: Demonstrates debouncing 8 keys. The state of the eight keys is sampled four times using a timer interrupt. If a key is pressed longer than four seconds, the corresponding bit in the key_press global variable is set. The main loop checks if a bit is set in this global variable and resets the bit. Pressing the key connected to PIND2 increments a counter, while pressing the key connected to PIND3 decrements the counter. The value of this counter is displayed using LEDs on PORTB.

*****************************************************************************/

#include #include #include #include

#ifndef CTC1 #define CTC1 WGM12 // for compatibility with ATmega #endif

#define XTAL 4000000L // Crystal frequency in Hz #define DEBOUNCE 200L // debounce clock 200Hz =

5msec

/* * Module global variable, informs the main programm when a key is pressed. * This variable must be declared 'volatile, since it is accessed from * both interrupt und main loop. */ static volatile uint8_t key_press;

SIGNAL (SIG_OUTPUT_COMPARE1A) { static uint8_t key_state; // debounced and inverted key state: static uint8_t ct0, ct1; // holds two bit counter for each key uint8_t i;

/* * read current state of keys (active-low), * clear corresponding bit in i when key has changed */ i = key_state ^ ~PIND; // key changed ? /* * ct0 and ct1 form a two bit counter for each key, * where ct0 holds LSB and ct1 holds MSB * After a key is pressed longer than four times the * sampling period, the corresponding bit in key_state is set */ ct0 = ~( ct0 & i ); // reset or count ct0 ct1 = (ct0 ^ ct1) & i; // reset or count ct1 i &= ct0 & ct1; // count until roll over ? key_state ^= i; // then toggle debounced state /* * To notify main program of pressed key, the correspondig bit * in global variable key_press is set. * The main loop needs to clear this bit */ key_press |= key_state & i; // 0->1: key press detect

}

int main( void ) { uint8_t count = 0; TCCR1B = _BV(CTC1) + _BV(CS10); // clear timer on compare match, no prescaler OCR1A = XTAL/DEBOUNCE; // timer = 5 msec TIMSK = _BV(OCIE1A); // enable Output Compare 1 overflow interrupt

DDRB = 0x00; // use all pins on PortD for input PORTD = 0xff; // with pull-up enabled

DDRB = 0xff; // use all pins on PortB for output PORTB = 0xff; // turn all LED off sei(); // enable interrupt

for(;;) { if (key_press & _BV(2) ) { // key 2 pressed, increment counter count++; PORTB = ~count; key_press = 0; } else if ( key_press & _BV(3) ) { // key 3 pressed, decrement counter count--; PORTB = ~count; key_press = 0; } }

}