slow peripherals and modelsim

Why don't you get my free LCD controller and take a look ?

Hi Info,

I am using it already. However displaying a character doesnt work, I can only reset the display.

Whats are the clk und the tick input for? Should both be clocked at 250 KHz?

I have removed the tick thing, now I just have a 250khz_clk on clk.

regards, Benjamin

I thought it was clear in the IP :

-- ------------------------------ Entity LCD_DRV is

-- ------------------------------ port( Clk : in std_logic; -- System Clock Rst : in std_logic; -- asynchronous Reset, active high Tick : in std_logic; -- Tick at 250 kHz (one clock cycle long)

It is a synchronous design, with only one clock domain.

• Clk is your one and only global Clock, any Frequency (above 1 Mhz) is fine.

• Tick is a one clock cycle long pulse repeated every 4 microseconds. A simple clock division does it.

Since you have all the commented code, you shouldn't have any trouble understanding how it works if you're curious.

Just feed the inputs with what is needed, but don't change any line in the code unless you fully understand how it works.

Below a test bench which should help you understand how it works. (I didn't verify that it was up-to-date with the version you have, but it should be pretty obvious to run this simulation)

-- tb_lcd.vhd

-- -----------------------------------

-- VHDL test bench for lcd_drv

-- -----------------------------------

-- (c) Bertrand Cuzeau

--

-- very simple simulation (no fancy command sent

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;

entity TB_LCD is end;

Architecture TEST of TB_LCD is

signal Clk : STD_LOGIC := '0'; signal Tick : STD_LOGIC := '0'; signal Dav : STD_LOGIC; signal Din : STD_LOGIC_VECTOR (7 downto 0); signal Rst : STD_LOGIC; signal Dout : STD_LOGIC_VECTOR (7 downto 0); signal Busy : STD_LOGIC; signal Lcd_En : STD_LOGIC; signal Lcd_Rw : STD_LOGIC; signal Lcd_Sel : STD_LOGIC;

-- 10 MHz clock for simulation constant Period : time := 100 ns; -- 10 times faster than reality to speed up simulation constant TickPeriod : time := 400 ns;

begin

process begin Tick Din, Dout=>Dout, Lcd_En=>Lcd_En, Lcd_Rw=>Lcd_Rw, Lcd_Sel=>Lcd_Sel, Rst=>Rst, Tick=>Tick );

process variable Data : std_logic_vector (7 downto 0) := x"5A"; begin Din '0'); Dav

Hi Info,

I forgot that the lcd_tick should only be period long... that was the problem :(

Does this function for generating lcd_tick out of a 10m and 250k clock look good? I havent tested it yet on the board, but it works in the simulator...

process (clk_250k,clk_10m) variable temp: bit; begin if clk_250k='1' and rising_edge(clk_250k) then lcd_tick

Hi Info,

I have implemented the LCD stuff now, but it doesnt work, I can not display characters. Have you tested it before on Hardware?

The datasheet of my lcd controller KS0066 does the initialization in different order....

regards, Benjamin

DAMN, my data bus was in the wrong order :)

This and other issues. Spend more time verifying and studying existing good code. Don't use a 250 kHz clock. Don't write processes like the one you posted. Understand what clock domains are and what issues they bring. And SIMULATE !

And, yes, I've used and tested my LCD controller on many different boards : Altera Apex, Altera Flex, Altera Cyclone, Tornado, Nios Cyclone, Nios Stratix, Lattice, Atmel FPSLIC, Xilinx XS40, Spartan II, Seytronix, Insight-Memec, and probably a few others. And 5 different makes of LCD modules. (HD74780 compatible, OTOM)

Read and re-read :

Tick generation doesn't seem difficult :

-- ----------------------------

-- 1 us, 4us & 10 us Tickers

-- ----------------------------

process (Clk, Rst) begin if Rst='1' then Div1

Hi Info,

difficult is a relativ word (my age in the FPGA world is only 3 weeks). But the code looks nice :)

thanks, Benjamin