Slice equation in bitstream

not available fully, need write your RE tools to gain this info

you can try generate LL file, but that file doesnt have all the needed some need still heavy RE :(

Antti

i found the location in the bitstream, where 'result-column' can be found. when i use all 4 variables in the function, i can find exact these column of the truth table in the bitstream.

(A3*A1)+(A2*A4)

05 37 00 00 => 0000 0101 0011 0111 0000 0000 0000 0000 (is the same, as in the truth table)

but when i use less than 4 variables, the bits are not in the right order (but the number of 1's is correct)

(A1+A2)*A4

00 77 00 00 => 0000 0000 0111 0111 0000 0000 0000 0000 (in other order)

or

A1*A3:

05 05 00 00 => 0000 0101 0000 0101 0000 0000 0000 0000

Hey backatyou,

I first did this 20 years ago with Xilinx parts. I guess the method hasn't changed.

1) Make a design. 2) Generate bitstream. 3) Edit function generator in XACT, sorry, FPGA editor. 4) Generate bitstream. 5) See what's changed from 2).

Not exactly rocket science, but effective nonetheless. You'll find the CLBs/Slices distributed regularly throughout the bitstream, I bet.

HTH., Syms.

yes, that's the way i go. but don't understand, why the order changes, when i use less than 4 variables ....

the LUT inputs are swapped randomly duting PR so that explains why the appear in different places think there are some settings to free LUT inputs but that may not always work

Antti

So, firstly, there only 16 bits in the LUT, right. You've written 16. So, let's look at just the first 16 bits of your truth table. In the second example, the A3 bit is 'don't care' so the equation implemented is :- ((A1+A2)*A4 * A3) + ((A1+A2)*A4 * ~A3)

HTH., Syms.

Whoops, correction above!

yes, 16 bits, i know. but the tip with the don't cares is great. thanks

hmm, but that doesn't explain why the bits have a different position. or i don't understand.

the mapper can swap LUT input at will, as long as the logic function remains the same

Antti

I believe they're in the right position. From left to right the bits represent ( ~A1 * ~A2 * ~A3 * ~A4 ) + ( A1 * ~A2 * ~A3 * ~A4 ) + ( ~A1 * A2 * ~A3 * ~A4 ) + ( A1 * A2 * ~A3 * ~A4 ) + ( ~A1 * ~A2 * A3 * ~A4 ) + ( A1 * ~A2 * A3 * ~A4 ) + ( ~A1 * A2 * A3 * ~A4 ) + ( A1 * A2 * A3 * ~A4 ) + ( ~A1 * ~A2 * ~A3 * A4 ) + ( A1 * ~A2 * ~A3 * A4 ) + ( ~A1 * A2 * ~A3 * A4 ) + ( A1 * A2 * ~A3 * A4 ) + ( ~A1 * ~A2 * A3 * A4 ) + ( A1 * ~A2 * A3 * A4 ) + ( ~A1 * A2 * A3 * A4 ) + ( A1 * A2 * A3 * A4 )

So, your equation is (A1+A2)*A4, which we re-write as ((A1+A2)*A4 * A3) + ((A1+A2)*A4 * ~A3) to include A3, can be re-written as

( A1 * ~A2 * ~A3 * A4 ) + ( ~A1 * A2 * ~A3 * A4 ) + ( A1 * A2 * ~A3 * A4 ) + ( A1 * ~A2 * A3 * A4 ) + ( ~A1 * A2 * A3 * A4 ) + ( A1 * A2 * A3 * A4 )

0000 0000 0111 0111

TaaDaa!

HTH., Syms.

cool thanks, let me think about it :)

hmm, but that is not the order of my truth table. i want to have something like this: 0000 0101 0101 0101

A1 A2 A3 A4 (A1+A2)*A4

0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1

Hi Stefan, Which is the same as this:-

A4 A3 A2 A1 (A1+A2)*A4 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1

Try drinking more coffee! ;-)

Cheers, Syms.