slave serial configuration of Vertex FPGA using a microcontroller

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hi

I want to configure a vertex FPGA using a PIC microcontroller in the
slave serial mode .

I am simply doing the following steps while configuring.
1.Hold prog_b pin low for some time to clear the configuration memory
2.Release prog_b pin
3.Send a high on init_b pin
4.Send the data serially bit by bit at the rising edge of each clock
pulse
5.Once the done pin high release the din pin

Is it the correct procedure


Re: slave serial configuration of Vertex FPGA using a microcontroller
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Check the data sheet, but I think INIT is an output from the FPGA.
HTH, Syms.



Re: slave serial configuration of Vertex FPGA using a microcontroller
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INIT (active low) is indeed an I/O, normally considered open drain
during configuration.  Depending on the part, it may be a dedicated
pin or turn into user I/O after config.  During config, the FPGA
drives INIT low from the time prog_b is asserted until it has
finished initialization.  You must wait for INIT to go "high"
(requires a pullup) before starting to clock the bitstream in.
INIT may also be driven low by the FPGA when it detects a CRC
error in the bitstream.  It is good to periodically check for
this while sending the bitstream.

INIT can also be an input to the FPGA, although this mostly
applies to master configuration modes.  Holding INIT low
externally will prevent the FPGA from self-configuration
when the mode pins are set for one of the master modes.  This
is useful when you want to load the part by JTAG, or force
the part to wait for some other reason after power up.

Last point.  Unless you change the default settings for bitstream
generation, you usually need at least 2 CCLK cycles after DONE
goes high to ensure startup of the FPGA.  Often you get these
for free if you send to the end of the generated bitstream data,
which is stored as bytes, however it is not guaranteed.  If you
run out of data from the .bit file, continue sending 1's on the
DIN pin.

HTH,
Gabor


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