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Skew between the output of a DCM ?

Hi,

I remember reading a few lines on this newsgroup about the fact that a DLL in a Virtex might not be able to handle a negligible skew between two outputs (clk0 and clk2X for instance) in some situations like a heavy loading difference between the two clock trees with maybe an important (but in the datasheet spec ?) jitter on the input clock. Ever since I read this I did not consider I could change from one clock domain to the other without special care. Has anyone something new concerning these potential cases ? If there is still a possibility does it apply only to Virtex or also to Virtex II ? The reason I ask is that the designs coming up are running faster and faster making it more difficult to consider changing clock domains with some extra precaution. Thanks,

JF

Reply to
jean-francois hasson
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The new version of Xilinx tools (6.1i and on) appear to be doing a more complete job on this analysis. The biggest problem earlier was the effect of input jitter on the DCM that couldn't be accounted for. Uneven loading on the clock nets was also an issue. Now the tools allow an INPUT_JITTER constraint to go along with your specified period and duty cycle. Also with the automated elimination of hold-time violations, it looks like the tools are filling in for the corner cases of design as long as we, the designers, give the tool the right info.

I'm now happier making the transition between same-edge clock domains without special treatment though I know where to look first if my design starts to misbehave.

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Reply to
John_H

The input_jitter constraint does not factor in jitter caused skew between clock nets. It only decreases the available cycle time in your period constraint to account for cycle to cycle variations (jitter) in the clock for that net. I don't know if the VirtexII suffers to the same degree or not (and I haven't chanced it) from DLL output spreading due to input jitter.

Safe cross> The new version of Xilinx tools (6.1i and on) appear to be doing a more

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

Hi,

I agree with the fact that crossing clock domains with special care is still possible even with higher clock frequencies. However, I believe some designs involving the Virtex II Pro cross clock boundaries (300 MHz to 100 MHz and the opposite) without concern about skew. Does that mean that the skew is negligible compared to propagation delay by construction of the Virtex II Pro ? Would it be the same for Virtex II ?

JF Hasson

"Ray Andraka" a écrit dans le message de news: snipped-for-privacy@andraka.com...

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Reply to
jean-francois hasson

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
formatting link

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

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