Skew between signals

"Michel Bieleveld" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

Sure, we are talking about real world, synthesizable HDL. The delay statements in VHDL are for simulation only. VHDL is concurrent, statements are processed in parallel as fast as possible (given by the target technology).

Hope is good, but basic understading of things is better. So how do you think such a thing might be possible.?? Adding a RC-Filter to an IO? There are serval tricks to get a more or less usefull workaround, but a reliable and safe way is to use a clock (and maybe the inverted edge). Nothing wrong with this. You can "adjust" the phase relation also by setting the IO driver to different driving strength and slew rates, but this is IMHO not a clean way (phase will vary with VCC and temperature)

Regrads Falk

if you want WE to toggle after CE you have two states not one (If you think of your design as a state machine). So doubling the clk is the best solution. That way you'll have WE toggle on one clk edge and CE toggle on the next.

It's not the answer you wanted to hear, but i think it is the way that will get you the most consistant results.

Eric

What Eric is suggesting is the cleanest way to do things.

Another alternative without going thru re designing logic too much is to use DCM to generate half frequency clk phase shifted by what ever delay you want. Use that clock as a gate to your WE. This will cause bad output times on you WE and could be a concern if you are planning to run at very high speeds and there is no margin to play with (if board delay plus set up times plus clk to q are barely meeting).

Else if you are generating WE thru a flop, things are still easier. Use DCM to generate same frequency clk as your core clk, delay phase shift by whatever amount you want and use that to clock your WE.

Hope all these help,

Regards,

Purvesh

Eric wrote:

that

You could make the CE signal bidirectional and use the fed back signal from the CE pin to gate the trailing edge of the WE signal.

WE out: std_logic; CE inout: std_logic;

CE

Thanks for the suggestions !

I am using a spartan 2E so i guess that DCM is not an option for me.

Currently, which also works, I am using an area constraint to put the logic closer to one pin than the other. In this way everything is "schedules" as i want to. I was hoping for a similiar and cleaner result by using some kind of timing constraint.

I imagine that this constraint would accept a minimum of delay compared to another signal. If this delay after synthesis is not met i would expect that aditional logic is place between pad and signal to delay the logic.

Thanks all for your input !

With regards,

Michel Bieleveld.

"Michel Bieleveld" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

The spartan-IIE has the DLL, which can do phase shifts of 90, 180, 270 degree (provided that the clock frequency is >25 MHz) You can use a 90 degree phase shifted clock to fix the delay in a reliable way.

Forget about such crap. This was a nasty (but often working) trick in the good ole, TTL days. No real option anymore.

Regards Falk