single pad to pad timing in ISE

I am trying to constrain a single path through my V4 fpga in ISE 6.3. In the VHDL source it simply connects an input pin to an output pin:

SER_Clock

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Anonymous
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the

WARNING:Timing:2666 - Constraint ignored: TS_P2P = MAXDELAY FROM TIMEGRP "Sclk_in_dec" TO TIMEGRP "Ser_Clock" 5 nS ;

Anyone know how to do this properly for a signle path? I've tried the "from PADS to PADS" global constraint but it is too restrictive for what I need.

Thanks, Clark

Reply to
Anonymous

Form your two timegroups using the instance names for the two iobs: INST "a" TNM = "In_Pad"; INST "b" TNM = "Out_Pad"; This can be done under the advanced tab of the constraints editor. Use whatever instance names your pads wind up with, instead of the "a" and "b" I show here. Then your FROM-TO timespec will work: TIMESPEC "TS_A2B" = FROM "In_Pad" TO "Out_Pad" 7 ns;

Note that the TNM_NET grouping constraint fans (traces) forward, not backwards, and will not include the pad that sources the net, and thus your original attempt does not produce a meaningful constraint. Use the Timing Analyzer tool to produce a report of your timegroups to see exactly what pins are included in your original timegroups if you're not sure how timegroup formation works.

Reply to
JustJohn

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