Single ended interface at 70Mhz for FPGAs

I'd go for external LVDS transceivers. They are very very cheap, made for this purpose and will save you a lot of headaches.

LVCMOS will be fine @ 70MHz. Your backplane should have a ground plane. Use appropriate terminations at the FPGAs. Look into the DCI stuff. Simulate it w/hyperlynx or similar.

Does this have to pass any EMC tests ? Will you need any headroom, or will the Bus NEVER be faster than 70Mhz ? There are also 4 bit busses : The intel LPC and QuadSPI use fewer pins.

-jg

Which FPGA(s) are you using? Even if you don't have MGT's available you could run your bus at twice or possibly even 4 times the speed while using LVDS. This way you could even save some pins. You could even employ DDR for more savings :)

/Mikhail

If you were trying to run at 210 MHz, I'd see where you might need to be more careful. You can use virtually any logic standard to get 70 MHz operation over 10 inches.

Since you're point-to-point, I'd suggest using source-series termination which is simply adding a resistor to your front end so your driver impedance plus resistor roughly matches the characteristic impedance of your PC board trace. Simon mentioned you need a ground plane; to get a good impedance without huge crosstalk and other problems, the ground plane is integral to any solid design driven with high edge-rate signals.

When you drive a source-terminated signal to VCCIO, the source impedance looks like a resistor divider into the instantaneous load of the transmission line that's about 2ns long on your PC board. While a half-amplitude signal may seem bad conceptually, when the signal reaches the nearly open end of the PC trace, the voltage level doubles as a reflection heads back to the driver. When the reflection finally hits the driver 4ns after the signal starts driving, the voltage level establishes to right around VCCIO with little or no drive current, hence minimal further activity on the line. If you used a heavy drive current without a resistor, the reflection would be much higher than VCCIO and the driver's protection diode would have to swallow a large amount of current for 4ns (round trip time). Not recommended.

A single resistor is cheap and easy. LVCMOS and LVTTL give you a broad choice of drive currents. If you wanted to look through the IBIS models for the "best" source impedance match to your PC trace and even *skip* the source series resistor, you'd work well. The tolerance on the drive current at half voltage is sloppy enough that driving harder with a series resistor gives you a more consistent source impedance.

Once you get the basics of source series terminations under your belt, the use can be quick and easy in future designs and your signal fidelity will thank you. If you probe this signal to see what it looks like, do so as close to the receiver pin as possible since you'll see the full voltage swing there rather than a couple inches away where you'll see the incident 1/2 voltage before the reflection brings the voltage back to VCCIO.

If you use a multi-drop bus instead, this approach is not advised without further investigation and simulation. For a bidirectional bus, the approach is still valid with the series resistor on each end. An open with a series resistor still looks pretty much like an open. The RC time constant of your receiver will be higher but you're talking a very few pF parasitics into a resistor typically 22-49 ohms; both directions look like source series terminated signals.

This stuff is great. I would have *no* qualms running a 200 MHz TTL bus with properly selected termination schemes.

- John_H

This is proprietary bus and it would not run greater than 70Mhz, but it is bi-directional bus.

-- Goli