"simultaneously switching output"

Dear MWJ, What annoys me is that you know how to use Google to post to usenet, and yet seem unable to carry out a basic search of the WWW for information. It's like going to the pub, and then shouting out of the window to ask people in the street to come in, go to the bar, and buy you a free beer. Sheesh. Hope this helps, Syms.

new to FPGA, so id like to ask what is "simultaneously switching

Simultanious Switching Outputs (SSO) is (as you'd expect) to do with what happens then mutliple output pins of a device change simultaniously. Since each IO will consume power to change state (due to driving external capacitance), when lots of IOs change state simultaniously the transient power requirements can be quite demanding and cause Vcc sag/ ground bounce. The effects of SSO can be mitigated with a good decoupling network, good PSU design, turning down drive strengths, reducing simultaniously switching ouputs, and probably other things I've forgotten. As already pointed out there is alot of information on this available online, and Xilinx cover the issue in detail.

Rob

Hi Rob, Not just external capacitance, but internal also. FPGAs tend to support a lot of output standards. For example, some Xilinx FPGAs claim a drive strength of 24 mA. The penalty paid for this flexibility is that it requires fairly hefty FETs which have a fairly large drain-source capacitance (Cds), leading to a Cpin of up to 10pF. This Cds needs charging by the output when it switches. The output drive standard is adjustable, as far as I can make out, by having several FETs in parallel, and switching on enough FETs to achieve the desired drive. Of course, all the FETs not being used in the lower drive strengths still present their Cds, which needs charging. Naturally, at lower drive strengths this charging current is lower and is so spread out over a longer time period, all of which gives the PDS a better chance of keeping the rails up, but the energy loss in the internal parasitic capacitance is the same no matter what drive strength is used. I point this out because this parasitic FPGA pin capacitance is often the dominant loading on a FPGA output pin, cf a memory device that may have a Cpin on an address input of only 2.5pF. HTH., Syms.