Maybe I'm reading/understanding it incorrectly - it looks to me that there' s an always @ (posedge(clk)) dependency for writes - but I'm relatively fin e with that - I won't need the data until the next clock anyway if I'm writ ing, because that's how the 6502 worked.
For reads, it looked to me as though it used always @ (*), and I (perhaps i ncorrectly) thought that would get me the results on the module's data bus as soon as the 'address' lines changed.
As for why to change it, I don't like it when I don't understand the error/ info messages the tool is giving me. Given my (relatively limited) understa nding of what the synthesis tool is actually *doing* under the hood, it pro bably means I'm not getting what I actually want, or if I am, it's in some highly-inefficient manner. Your comment about inferring extra adders unnece ssarily is pretty relevant I feel :)
It does tie me to a single write/read per clock, whereas I could set N regi sters per clock (and thus "push" 3 elements onto the stack for the BRK inst ruction in a single clock for example), but I'm actually ok with that too, I think. The 6502 only had 1 databus, so *it* took multiple clocks to do mu ltiple writes as well.
Its entirely possible my understanding of the module is flawed. I'm happy t o be corrected :)
Cheers Simon