this code causes 100% simulation failure.
Rx
- posted
20 years ago
simulation stops preliminarily
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- Vote on answer
- posted
20 years ago
Are you 100% sure that AVAIL is making a transition to '1' at some time after the previous wait has finished?
Don't forget that "wait until" is EDGE triggered. It will wait forever if AVAIL is stuck at '1'.
-- Jonathan Bromley, Consultant
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- Vote on answer
- posted
20 years ago
And to add to what Jonathan said, if you want to do a level check, do the following:
if (Avail /= '1') then wait until AVAIL = '1'; end if ;
Read wait as stop. Wait always stops for at least one delta cycle.
Cheers, Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~