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Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a

I am attempting to simulate a very basic system built with Xilinx EDK

7.1.02i, using VHDL. After generating the ModelSim specific compiler scripts, I can execute a do system.do, which works okay, but when I execute the vsim system command I get the following results. I have had similar problems when trying to do a Verilog/VHDL mixed simulation system. Looking around on the Xilinx web site, I see that someone else has had a similar problem
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snipped-for-privacy@233.ec snipped-for-privacy@.eef9bc), but I did not see any responses or suggestions.

Any help would be appreciated.

Thanks, Brian

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ModelSim> vsim system_conf system # vsim system_conf system # Loading c:\Modeltech_6.1a\win32/../std.standard # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_1164(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.vcomponents # Loading c:\Modeltech_6.1a\win32/../std.textio(body) # Loading c:\Modeltech_6.1a\win32/../ieee.vital_timing(body) # Loading work.system_conf # Loading work.system(structure) # Loading work.microblaze_0_wrapper(structure) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze_isa # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_arith(body) # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_unsigned(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze_types(body) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze(imp) # Loading c:\Modeltech_6.1a\win32/../ieee.numeric_std(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.decode(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.prefetch_buffer(imp) #

Loading c:\Modeltech_6.1a\win32/../ieee.vital_primitives(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.vpkg(body) # ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns). # Time: 0 ns Iteration: 0 Region: /system/microblaze_0/microblaze_0/decode_i/prefetch_buffer_i/using_fpga/prefetch_buffers__0/srl16e_i #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.srl16e(srl16e_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxcy_l(muxcy_l_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.xorcy(xorcy_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fds(fds_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdr(fdr_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut4(lut4_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut3(lut3_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdrse(fdrse_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdre(fdre_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdse(fdse_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.data_flow(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.register_file(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.register_file_bit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.ram32x1d(ram32x1d_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.operand_select(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.operand_select_bit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxf5(muxf5_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fde(fde_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut2(lut2_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.alu(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.alu_bit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.mult_and(mult_and_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.shift_logic_module(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.shift_logic_bit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mul_unit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.mult18x18s(mult18x18s_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.result_mux(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.result_mux_bit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fd(fd_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.zero_detect(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.msr_reg(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.msr_reg_bit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.pc_module(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.pc_bit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.byte_doublet_handle(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.data_read_steering(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mux4_8(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mux2_8(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.dopb_interface(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxcy(muxcy_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.opb_data_mux(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.iopb_interface(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.debug(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.address_hit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.address_data_hit(imp) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.fsl_module(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.instr_mux(imp) # Loading work.mb_opb_wrapper(structure) # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_signed(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/proc_utils_v1_00_a/.conv_funs_pkg(body) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arb_pkg(body) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_v20_v1_10_c/.opb_v20(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.srl16(srl16_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.or_gate(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arbiter(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arbiter_core(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.watchdog_timer(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.control_register_logic(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.priority_register_logic(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.priority_reg(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.arbitration_logic(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.park_lock_logic(implementation) #

Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/proc_common_v2_00_a/.or_bits(implementation) #

** Fatal: INTERNAL ERROR in reset_trigger_process(). # Time: 0 ns Iteration: 0 Process: /system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process File: C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd #

FATAL ERROR while loading design # Error loading design

Reply to
Brian C. Van Essen
Loading thread data ...

/system/microblaze_0/microblaze_0/decode_i/prefetch_buffer_i/using_fpga/prefetch_buffers__0/srl16e_i

Have you tried running with the simulation resolution set to 'ps'? That would normally be done in the modelsim.ini file or the project.mpf file, by changing the "Resolution" line.

/system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd

These kinds of problems can be difficult to debug in Modelsim. I try to narrow down the problem by trying to load individual pieces of the project. That is, when you get the "Load Design" dialog, pick an entity for just a portion of the design. You are not going to simulate the pieces of the design, because all you care about for this testing is whether they will simply load.

For example, pick the entity that is in park_lock_logic.vhd. If that loads, then the problem is elsewhere. If not, the problem is either that entity or one of the entities contained within it. It is a bit of a trial and error method, but I have always been able to find the problem file with this method.

Reply to
Duane Clark

/system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd

Bring up park_lock_logic.vhd and find reset_trigger_process Check the declarations of all array indexes used there.

I fixed a similar problem by changing an array index type from integer to natural.

-- Mike Treseler

Reply to
Mike Treseler

/system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd

Well, I have tried to find the reset_trigger_process in all of the libraries vhdl files, but was unable to. I am guessing that it is part of a library like unisim (which is commented to be a Xilinx library). If that is the case, then I am not sure how to correct it if the library is already compiled. Does anyone else have a working environment with these settings.

It is important to note that this error does not appear when using a system that only has a PowerPC. Thus, it seems isolated to a component required by the Microblaze.

Again, any more feedback would be wonderful.

-- Brian Van Essen

Reply to
Brian C. Van Essen

The unisim library source is in $XILINX/vhdl/src/unisims It does not come precompiled, but is compiled by the person that installed your Xilinx software. It does not contain that function.

Reply to
Duane Clark

Was there source code at: C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd ?

If you don't have the source, you can't debug it, only the owner can:

formatting link

Or if you have a Mentor Modelsim license open a case with them.

If you need IP by others, buy the source code.

-- Mike Treseler

Reply to
Mike Treseler

Experienced the same problem. It seems that it is a bug in 6.1a ModelSim version, because I've never faced a similar problem with the same EDK libraries in 5.x ModelSim versions.

However, the whole problem is in a VHDL construction that is somehow incorrectly interpreted by ModelSim when compiled with default (-O4) or higher optimization enabled. Here is a snippet of park_lock_logic.vhd (opb_arbiter_v1_02_e), which causes that FATAL ERROR:

GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate

-- ... skipped some code

-- Register the grant signals if registered grant outputs -- reset this register with park_fe REGGRNT_GEN: if (C_REG_GRANTS) generate REGGRNT_PROCESS: process (Clk, park_fe(i)) begin -- asynchronously reset when park negates if park_fe(i) = '1' then mgrant_reg_i(i)

Reply to
Jiri Bucek

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