I am attempting to simulate a very basic system built with Xilinx EDK
7.1.02i, using VHDL. After generating the ModelSim specific compiler scripts, I can execute a do system.do, which works okay, but when I execute the vsim system command I get the following results. I have had similar problems when trying to do a Verilog/VHDL mixed simulation system. Looking around on the Xilinx web site, I see that someone else has had a similar problemAny help would be appreciated.
Thanks, Brian
-------------
ModelSim> vsim system_conf system # vsim system_conf system # Loading c:\Modeltech_6.1a\win32/../std.standard # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_1164(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.vcomponents # Loading c:\Modeltech_6.1a\win32/../std.textio(body) # Loading c:\Modeltech_6.1a\win32/../ieee.vital_timing(body) # Loading work.system_conf # Loading work.system(structure) # Loading work.microblaze_0_wrapper(structure) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze_isa # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_arith(body) # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_unsigned(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze_types(body) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.microblaze(imp) # Loading c:\Modeltech_6.1a\win32/../ieee.numeric_std(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.decode(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.prefetch_buffer(imp) #
Loading c:\Modeltech_6.1a\win32/../ieee.vital_primitives(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.vpkg(body) # ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns). # Time: 0 ns Iteration: 0 Region: /system/microblaze_0/microblaze_0/decode_i/prefetch_buffer_i/using_fpga/prefetch_buffers__0/srl16e_i #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.srl16e(srl16e_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxcy_l(muxcy_l_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.xorcy(xorcy_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fds(fds_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdr(fdr_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut4(lut4_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut3(lut3_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdrse(fdrse_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdre(fdre_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fdse(fdse_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.data_flow(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.register_file(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.register_file_bit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.ram32x1d(ram32x1d_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.operand_select(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.operand_select_bit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxf5(muxf5_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fde(fde_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.lut2(lut2_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.alu(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.alu_bit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.mult_and(mult_and_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.shift_logic_module(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.shift_logic_bit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mul_unit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.mult18x18s(mult18x18s_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.result_mux(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.result_mux_bit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fd(fd_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.zero_detect(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.msr_reg(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.msr_reg_bit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.pc_module(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.pc_bit(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.byte_doublet_handle(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.data_read_steering(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mux4_8(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.mux2_8(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.dopb_interface(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.muxcy(muxcy_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.opb_data_mux(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.iopb_interface(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.debug(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.address_hit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.address_data_hit(imp) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.fsl_module(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/microblaze_v4_00_a/.instr_mux(imp) # Loading work.mb_opb_wrapper(structure) # Loading c:\Modeltech_6.1a\win32/../ieee.std_logic_signed(body) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/proc_utils_v1_00_a/.conv_funs_pkg(body) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arb_pkg(body) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_v20_v1_10_c/.opb_v20(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.srl16(srl16_v) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.or_gate(imp) # Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arbiter(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.opb_arbiter_core(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.watchdog_timer(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.control_register_logic(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.priority_register_logic(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.priority_reg(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.arbitration_logic(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.park_lock_logic(implementation) #
Loading Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/proc_common_v2_00_a/.or_bits(implementation) #
** Fatal: INTERNAL ERROR in reset_trigger_process(). # Time: 0 ns Iteration: 0 Process: /system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process File: C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd #FATAL ERROR while loading design # Error loading design