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- Simulation of PCIe at TLP level
- Svenn Are Bjerkem
March 24, 2017, 9:23 am
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Re: Simulation of PCIe at TLP level
There's multiple ways to tackle this. Since this is an FPGA group,
one assumes you're implementing this on an FPGA. Xilinx for example
will generate some sort of example design which you can run in your
favorite simulator, and watch your TLP packets pass by. Hack at it
and recode as you see fit.
Normally, if your implementing an PCIE endpoint within and FPGA,
the generated example will just insert an equivalent root complex
inside the testbench to manage the low-level PCIE negotiations, etc.
Other options include purchasing PCIE verification IP from a vendor.
There's many options here.
Other options include writing your own PCIE TLP source/sync models (at perhaps
a higher level), and tying that up in your testbench.
There's many options here to explore, all depending on your requirements.
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