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Simulation in modelsim.... Multiple Drivers.......

Hi all... i have been trying to simulate some code in which there is a data bus that is declared to be of INOUT type. I have simulated my VHDL code and for both read and write operations it works fine, also the data bus gets tri-stated (Z) when not in use. Now this simulation was done by directly putting the values of signals in the ModelSim environment. Then I thought to write a testbench to simulate the same. In this case when I write some data on the databus it does not get tri-stated when not in use. So i tried to debug the problem and found that since in my testbench I am forcing some value on the bus say '3B' and also in code i force 'Z' when not in use, then STD_LOGIC being a resolved type resolves the value and gives '3B' since 'Z' has got least priority. Why it worked directly on ModelSim environment was bcoz i was "Depositing" the value on bus and not "Freezing" it. If i freeze the value there then in that case also i cud not make the bus tri-stated.

So i would like to know how in our testbench we can write code such that i can see all the correct results. I think in practice this will work fine but it's better if in simulation also we can see the desired results. Hope somebody can help. Thanx a lot

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CODE_IS_BAD
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Your test bench also needs to behave properly and put a 'Z' out when it has relenquished the control of the bus and not continue forcing '3B'.

Brijesh

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Brijesh

hello Brijesh... yes yaar i have already done that... But i wanted to know wether there is any mechanism with which we can also u know 'deposit' values instead of 'freezing' it as we do in modelsim. Waise thanx again for the suggestion.

Puneet

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CODE_IS_BAD

In a VHDL testbench there is no concept of "deposit" or "freeze".

Your testbench has to simulate the behavior of the other participants to the data bus. This means, the testbench has to drive the bus with something like "3B" when it wants to write to the data bus. Immediately after the DUT (device under test = your code you want to test) has read the data or at least shortly before your DUT has to write the bus itself, the testbench must free the bus by tri-stating the testbench (writing 'Z' to the bus). This follows exactly the behavior of the electronics, your testbench has to write 'Z' to the data bus when the electronic of the other bus participants disables their output drivers. The exact time this tri-stating is done depends on the electronic you want to simulate.

Klaus

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Klaus Falser

Hi Klaus... Ok... this was something i was not knowing about. I thought there might be just some way that i may not be knowing about. Thanx for the answer. But i feel in VHDL 200X, i.e. the next version coming up, in that i think they r planning to include these things also. regards, puneet

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