Hi,
I have some problems when using two clock domains in my design. My main clock works at a frequency of 60 Mhz. The clock port is routed to the input port of the internal DLL which provides two clock sources, one of the same frequency (60 Mhz) and the other of 20Mhz.
There is a rising edge detector FF excited with 20 Mhz clock
re_detect: block is signal aux : std_logic; begin process( rst, clk_20 ) begin if ( rst = '1' ) then aux
"arkaitz" escribió en el mensaje news: snipped-for-privacy@posting.google.com...
hadnt you posted this problem before?
what do you mean by "synchronized"? to what? besides "input" should be stable before (and after) the clock edge, they shouldnt change at the same time (if that's what you meant with "synchronised") and i would have thought that a glitch is what you're getting with those "0 ps" pulses
you could write it otherwise, like
elsif ( clk_60'event and clk = '1' ) then if ( re_edge = '1') then out mean is asserted and dessaserted in the same simulation step and in
dont you think you should correct that? do you think that's a good sign? besides that's completely normal from your "re_edge
Hi, include re_edge in sensitivity list.
Hi Paris,
First of all, thanks for answering to my message. I'll try to answer to all of your questions.
Yes and no. The post I wrote before had to do a lot with this one but now I think that the problem comes from another source.
The "input" signal is an asynchronous input port and it must be synched before I use in my design, just to avoid metastability and glitches. Even if its asynchronous it's active during several clock hundreds of clock cycles. Here you are the synch:
entity top port ( ... in : in std_logic; ... ); end top;
architecture arch of top is ... signal input : std_logic; signal i_filter : std_logic_vector(1 downto 0); ... begin process ( rst, clk ) begin if ( rst = '1' ) then i_filter '0'); elsif ( clk'event and clk = '1' ) then i_filter(0) elsif ( clk_60'event and clk = '1' ) then
yes, that's true, but the result would be the same.
You want out to be low for 3 clk_60 cycles (1 clk_20) when input rise.
To avoid problem of passing from one clk domain to the other (because both clks must be balanced at both aux and out registers), you can do this if input high time and low time are both at least 3 clk_60 cycles width all the time and it's synchronous with clk_60.
signal aux : std_logic_vector(2 downto 0);
process( rst, clk_60 ) begin if ( rst = '1' ) then aux '0'); elsif ( clk_60 = '1' and clk_60'event ) then aux
"arkaitz" escribió en el mensaje news: snipped-for-privacy@posting.google.com...
same
"0
if you want to sync to avoid metastability, maybe you could check out
no it wouldnt, cause in your design, there's a problem is "re_edge" and "input" are both high this one only if re_edge is not high, the second statement (the elsif) would be executed, in your code, both if's will always execute
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.