Simulating Post-Synthesis Model on Xilinx FPGA

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Hi there,

I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a
Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
XC2S300E device).

I'm very new in FPGAs and hardware design, and if you could help, that
would be great.

Is there any way for me to run a simulation on the post-synthesis model
of my design? I know that with Xilinx ISE, we can run simulations on
behavioural models, post-translate, post-map and post-PAR models. What
about the synthesised model?

Please help.

Thanks very much in advance.

Regards,
Chloe


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Hi there,

I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a
Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
XC2S300E device).

I'm very new in FPGAs and hardware design, and if you could help, that
would be great.

Is there any way for me to run a simulation on the post-synthesis model
of my design? I know that with Xilinx ISE, we can run simulations on
behavioural models, post-translate, post-map and post-PAR models. What
about the synthesised model?

Please help.

Thanks very much in advance.

Regards,
Chloe


Re: Simulating Post-Synthesis Model on Xilinx FPGA
(translate + map + PAR) == synthesis

If you're simulating post-PAR, you -are- simulating the synthesised
model


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Thanks for your reply.

I would actually like to simulate the verilog model AFTER synthesis but
BEFORE translate. Is there any way to do that?  

Thanks in advance.


Re: Simulating Post-Synthesis Model on Xilinx FPGA
I'll try to be a little clearer:

Synthesis is translate and map.  After synthesis would be after
translate and map.  You can't be after synthesis and before translate
because translate is the 1st step in synthesis.

It's sort of like saying "After I get there, but before I leave".

What exactly are you looking for, anyway?


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Oh really? Apologies for my ignorance. This is my first time using an
FPGA's synthesis tool, so I didn't know that synthesis actually meant
translate and map. I thought translate and map was using the LOCed pin
assignments and inserting that with the synthesised design onto the
FPGA. I previously dealt with Synopsys synthesis tool, Design Compiler,
so it's a little different from FPGA synthesis.

Anyways, I am having a little trouble with the design on FPGA. When I
simulated the behavioural model on ModelSim, the results are correct.
However, after synthesis, when I ran a simulation on the post-translate
verilog model, the outputs were wrong. Ditto for post-map and post-PAR
verilog models.

I'm at my wits' end, because I've been working on the problem for quite
some time now, and yet, I  still couldn not find the root of the
problem. There were no errors in my synthesis report, translate report,
map report and PAR report. There were no timing violations either.

Any suggestions for an FPGA rookie like me?

Oh, by the way, I think it's more like "After I leave, but before I get
there" ;)

Thanks in advance.


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Quoted text here. Click to load it

Post your code.

         -- Mike Treseler

Re: Simulating Post-Synthesis Model on Xilinx FPGA
Mike: Very sorry, it's propriety information, so I cannot post my code
here. I know it's silly for me to ask for help without me having to
post my code here, but I thought with everyone's experience with FPGAs,
I could get some suggestions or comments from y'all, or maybe some of
your own experience in a similar problem and how you came about solving
it.

Apologies again, and thanks for the suggestions given.

Chloe.


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Quoted text here. Click to load it

Uh, no.  Synthesis is conversion from the HDL to an edif netlist or the
equivalent xilinx proprietary.  Translation is the first step in the
implementation tools, followed by map and then place and route.  The
boundary between synthesis and translate is a fairly common place to do
simulation since it simulates the synthesized netlist without having to
do the slower timing model.  Translate is also the entry point for
designs synthesized (or otherwise produced) from other tool chains.


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Chloe,
  When I look at the GUI for ISE 7.1i sp4, Under Synthesize - XST, I
see an item to Generate Post-Synthesis Simulation Model.  Is that what
you want?  I normally do not do a simulation at this intermediate
level, so I don't have any information concerning the gotcha's
involved.
  It looks like it will output a file compatible with Modelsim's
Verilog simulator.
  
Hope this helps,

Newman


Re: Simulating Post-Synthesis Model on Xilinx FPGA
Newman: Thanks for the suggestion. I actually tried taking out the
synthesised output file and running a simulation on it with a testbench
on Modelsim. I imported the FPGA library into Modelsim as well, with
the cell library used in the synthesised model. Unfortunately, I
encounted some fatal errors which I do not understand. The fatal error
seems to be connected with the library, instead of the design.

Normally I would just do a simulation beyond the translation stage, but
since I had no idea where the problem is in the post-translate verilog
model, I thought I'd run a simulation on synthesis and see if the
problem occured there as well. I'm trying to eliminate as many factors
as I can in finding the root of the problem.

Anyways, according to ghel, the translated model IS the synthesised
model, so I guess I'll work with that instead.

Thanks again :)


Re: Simulating Post-Synthesis Model on Xilinx FPGA

Quoted text here. Click to load it

You can, but you'll need to get either the mapped HDL output or an edif
netlist (and a simulator such as Aldec that will simulate an edif
netlist).  I think the native XST output is the xilinx proprietary
netlist format, so you'll have to figure out the switches to get either
the mapped VHDL/Verilog or edif output.  I use synplify, and for that
you just turn on the mapped vhdl/verilog, and it writes the structural
netlist to an output file in the selected language.

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