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Simulating post par simulation model

Hello all, I am trying to simulate a post par simulation model of a design which contains block RAMs. The source code is simulated using the simulation block RAM model. And the internal memory is accessed using '.' operator. This suceessfully simulated. But when i tried to imulte the post par model an error occured. I have used the X_ library files for simulation. Initially i simulted and only accessed the output signals. This version simulated successfully. But when i tried to access the internal memory using . operator. At the time of loading the design an error occured. It reported no load error for a mux which is not part of the RAM. Found no reation between the error reported mux and the RAM. Why this condition. I just tried to access the RAM in the simulation. What could be the problem. regards Sumesh

Reply to
vssumesh
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accessing the internal memory with '.' (verilog's hierarchical access operator i am assuming) will not work after p&r. you have to use the memory as a memory ie give an address at its ports and get the data from the data ports. as you say "block ram model" is just a model.

Reply to
m

But why?. I am a beginer in this... I thought that the post par model is only a verlog description (with delay for component and routing included). Why cant we access an internal variable in the simulation?

Reply to
vssumesh

Or please tell me a method to combine two internal variables (mem in the RAMB16 block). Situation is i have to xor mem variable from 16 RAMB16 blocks and show it as an array 32x64. I am able to view this through the waveform window.

Reply to
vssumesh

In the post par model i observed that the variables are started with '' sign. Also instantiations are also started with this sign like X_RAMB16 \RR/ram etc. Why this sign is in front of all variables ???

Reply to
vssumesh

Somebody please help me on this issue.... I am not able to compare the registers now.... please help

Reply to
vssumesh

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