I am working on a design involving 2 4028EX devices along with an external SRAM bank. Is there a way I can simulate both post-synthesis netlists together? I'm trying to find a way where I can model the memory and chip interconnects and then simulate the whole system. The devices are on a PCI card which is one if the reasons just using a larger chip isn't an option. Thanks
Of course you can do this. Generate post-synthesis (back-annotated) VHDL-Files and put them into a single structural VHDL design that connects them appropriately. In addition, you might need to model other things such as the memories and some PCI stub in your case. You would integrate this either directly into your top-level structural design or (better) create separate modules.
Regards, Mario
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