Simulating fixed point multiplica​tion using float ing point core v5.0 on Virtex-6 LX75T ISE 13.4

I used the floating point core v 5.0 to generate a multiplier for single precision multiplication and fixed point multiplication (custom width 16 bits with 11 bits fraction). I am able to successfully simulate and synthesize the floating point multiplier, but the fixed point core just fails. I am using ISIM to simulate the fixed point core.

select the Q point (11 bits fraction).

and I see my output as x0000, whereas I am supposed to see x018B (0.1933). I don't see the overflow or underflow signal going high.

It sounds like you may be looking at the wrong output bits of your multiplier. If you add something to the left of the radix point do you get a non-zero output?

-- Gabor

A multiplier with 16 bit inputs should generate a 32 bit product.

For addition, you likely would be adding two numbers with the same number of fractions bits, but for multiply they are often different. You have to select the appropriate fraction bits based on the fraction bits of the inputs.

-- glen