Hello all,
Whenever I need to look at a filter output (or any DSP core), I used to define a real signal and assign it to what I want to examine, roughly something like this:
dac_real_out
Hello all,
Whenever I need to look at a filter output (or any DSP core), I used to define a real signal and assign it to what I want to examine, roughly something like this:
dac_real_out
You can't *elaborate* (vsim) your design because the compiled work directory does not match the simulator you are using. Delete it and recompile (vcom) For modelsim, that is something like:
vdel -all vlib work vmap work work vcom
I like to write script like this to archive with the design.
I expect that is true. You are better off with a real hdl simulator in any case.
-- Mike Treseler
Thanks a lot Mike. Got sorted.
-Manny
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