Simulated Quartus II delays are much greater than measured

oopere schrieb:

Wrong. Always the opposite. The delay values given by the manufacturer (and used in simulation) are guaranteed values under worst case conditions. For CMOS these usually are:

- worst case input rise time (yes, gate delays depend on input slope)

- The lowest allowed VCC

- A rather high output loading (e.g. 50pF for PCI compliant outputs)

- The highest allowed temperature

- slowest chip on a wafer

- slowest wafer produced over time

If you have flip flops in your design:

- worst case clock arrival time for on chip clock skew and jitter

additionally for SOI chips:

- worst case signal history (delay depends on the last couple of transitions)

You are probably far away from worst case for most of these parameters, so you will always be faster in reality than in a worst case simulation.

On the contrary. For virtually all applications the slowest edge behaviour is what you want to simulate. For all other applications you need to do monte carlo simulation.

Kolja Sulimma

Thank you. I understand your points. I did not take into account that I am simulating the worst case scenario. However,

a) I still wonder if 15ns is a reasonable worst-case delay for a direct input to output connection (or for an input->not gate->output connection) for this kind of device. I have been trying to figure out which combination of t_xyzk?#? from the datasheet I should be adding in this case (have to say, without success)

b) It is surprising that the simulator tells that the direct connection exhibits greater delay than the inverted one. Perhaps this depends on which particular output pin is driven?

Any comments, anyone?

Pere

Sorry, this should be a Flex10K "EPF 10K10ATC144-3" device

That sounds like a bug - if you have checked that's what the design tools actually created.

ie What may have actually been created is a nett-non-inv path, and an nett-inv-path, and if the latter can be made by _removing_ an inverter, then the delays you report make sense. ( 400ps faster )

You can reality check your silicon, with a ring oscillator design. That can indicate how Vcc and Temperature affect delays, for example. Process variations are harder to get a handle on, but 3:1 ratios you seem to have, would be at the conservative (pessimistic) end of the range.

What can also result in that, is if vendors have faster speed grades and the slow one is a 'yield safety net', plus they round-up to the nearest 5ns, and they can also meet some competition point ( 15ns was a common spec point, years ago ) - combine all that, and you can get what looks like a very fat margin, especially on the trail-end devices.

Sometimes vendors have to keep labeling (eg) -15 parts, because that's what purchasing depts have 'locked in', and not because it has much to do with what the FABs produce :)

-jg

Jim Granville schrieb:

For what load are these delays specified? (Datasheet) What drive strength are you using? (Constraints File) Do the math: Driving a 50pF standard PCI load with a 2mA driver from 0 to 1.6V will take 40ns without any internal delay. Most FPGAs have programmable output drive strengths and logic families. Try changing your output to LVDS or GTL and see what delays you get.

Not at all. Because NMOS transistors are faster than PMOS transistors the fastest overall speed for a CMOS device is achieved if the falling transition of each gate is made faster than the rising transition.

(Page 2/11) This probably is the case for your output buffers. Try out what delays you get when simulating the opposite transition.

Also, for higher loads, circuits actual can get faster by adding gates to the path.

Kolja Sulimma