Hello,
? have a code like this and i have to use SSD for outputs.
module telephoneConversation(clock, reset, caller, callee, areaCode, startE nd, letter, display, leds); input clock, reset, caller,callee; input areaCode; // 0: city_A, 1: city_B input startEnd; // 0: start, 1: end input [2:0] letter; // a character (from the code) of 3 bits output reg [27:0] display; // 4 displays of each 7 bits output reg [7:0] leds; // represents the correctness of the guess reg [3:0] current_state; // current state of the circuitry reg [3:0] next_state; // next state of the circuitry reg [14:0] characterCount; // number of characters transferred reg [12:0] transitionCounter; // counter to wait in the states reg [1:0] areaCode_caller; reg [1:0] areaCode_callee; ? // additional registers
// sequential part - state transitions always @ (posedge clk or posedge rst) begin ? end
// combinational part - next state definitions always @ (*) begin ? end // sequential part - control registers always @ (posedge clk or posedge rst) begin ? end
// sequential part - outputs always @ (posedge clk or posedge rst) begin ? end
?endmodule
I have a ssd code like this
"`timescale 1ns / 1ps /////////////////////////////////////////////////////////////////////////// /////// // Company: // Engineer: // // Create Date: 19:32:18 01/04/2010 // Design Name: // Module Name: ssd // Project Name: // Target Devices: // Tool versions: // Description: This module drives the seven segment displays. It has got 4 different inputs // for the 4 digits on the board. It's inputs are not directly the bin ary numbers. // You need to convert 4-bit hex values to their seven segment display equivalents. // // a0,b0,c0,d0,e0,f0,g0 belongs to digit0, rigth most digit on the boa rd. // a1,b1,c1,d1,e1,f1,g1 belongs to digit1, 2. from the rigth digit on the board. // a2,b2,c2,d2,e2,f2,g2 belongs to digit2, 3. from the rigth digit on the board. // a3,b3,c3,d3,e3,f3,g3 belongs to digit3, left most digit on the boar d. // // The values that you connect to these inputs will appear on the disp lay digits. // Thus, you just need to make the appropriate connections and should not concern // about the rest. // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // /////////////////////////////////////////////////////////////////////////// /////// module ssd( clk, reset, a0,a1,a2,a3,b0,b1,b2,b3,c0,c1,c2,c3,d0,d1,d2,d3,e0, e1,e2,e3, f0,f1,f2,f3,g0,g1,g2,g3,a,b,c,d,e,f,g,an0,an1,an2,an3 );
input clk, reset;// set clock and reset as input(1 bit) input a0,a1,a2,a3,b0,b1,b2,b3,c0,c1,c2,c3,d0,d1,d2,d3,e0,e1,e2,e3,f0,f1,f2, f3,g0,g1,g2,g3;//set our display data as input(1 bit) output reg a,b,c,d,e,f,g,an0,an1,an2,an3;//set outputs also as registers (1 bit)
reg [2:0] state;//holds state number (3 bit) reg [14:0] counter;//counter to slow the input clock(15 bit)
//in this always block the speed of the clock reduced by 25000 times so tha t display works properly always @ (posedge clk) begin //state counter if(reset) begin //synchronus reset state