Simple state machine in CUPAL

I'm working on a Power-On-Jump GAL/SPLD for an 8080 machine. I'm trying to figure out how to write it using Sequence/Present/Next syntax. I'm not sure if a standard 22v10 GAL can handle what I need. I can also use a 750 from Atmel that is basically two 22v10s (I guess this means it has internal pinnodes?)

Here is the required flow. The state machine will have to wait for an input condition and then respond with an output action.

Inputs: RESET PDBIN

Outputs: DI7...0 CCDSB

I: RESET LOW O: DI7...0 output enable O: CCDSB LOW I: RESET HIGH (do not necessarily need to wait for) I: PDBIN HIGH

0: DI7...0 = C3 I: PDBIN LOW I: PDBIN HIGH O: DI7...0 = 00 I: PDBIN LOW I: PDBIN HIGH O: DI7...0 = FF I: PDBIN LOW O: DI7...0 output disable O: CCDSB HIGH

Then I would like for the state machine to start waiting for another reset.

I tried writing a Sequence/Present routine but the way I wrote it there were duplicated states. Does anyone have any pointers or suggestions on how I should attack this problem?

I have 8 other inputs that I did not mention. JMP15...8. Once I get the basic logic down I want to make the last byte sent reflect jumper settings (DI7...0 = JMP15...8)

Thanks, Grant

Reply to
logjam
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yes.

if it complains about duplicated states, you need to add some dummy state-bits, to make each state unique.

- above you seem to have 5 output choices, so you need 5 states, which is 3 state bits, at a minumum. DI7..0 seem to have no restrictions on value, so cannot be used for state variable saving, but CCDSB can be part of the state engine. So that means >= 2 more bits, and unless you can prune DI7..DI0 to DI6..DI0, you will need to use the ATF750CL, to get enough macrocells.

That needs to be added to your state sequence.

-jg

Reply to
Jim Granville

How do I learn the pinnode numbers of the burried flip flops in the ATF750? I can't find anything useful in the data sheet.

Grant

Jim Granville wrote:

Reply to
logjam

[sound of some very dusty archives being dug into...]

et voila : Snipped from an ATF750 CUPL file :

PIN 1 = PIN 2 = PIN 3 = PIN 4 = PIN 5 = PIN 6 = PIN 7 = PIN 8 = PIN 9 = PIN 10 = PIN 11 = PIN 13 =

/* Output Pin and No PIN 14 = PIN 15 = PIN 16 = PIN 17 = PIN 18 = PIN 19 = PIN 20 = PIN 21 = PIN 22 = PIN 23 =

PINNODE 25 = PINNODE 26 = PINNODE 27 = PINNODE 28 = PINNODE 29 = PINNODE 30 = PINNODE 31 = PINNODE 32 = PINNODE 33 = PINNODE 34 =

Reply to
Jim Granville

Thanks for the help! Here is what I came up with. It seems to work good (in the simulator!!!). I hope there are no glitches in the 8080 status signals...

Do you see anything I could have done to make the design better? I've included my .PLD and .SIM files.

.PLD file:

Name PowerOnJump ; PartNo 00 ; Date 8/15/2006 ; Revision 01 ; Designer Engineer ; Company Stockly Electronics ; Assembly None ; Location ; Device v750c ;

/*** INPUT PINS ********************** DESCRIPTION

****************************/ PIN 1 = CLK16M ; /* 16MHz Clock */ PIN 2 = pRESET ; /* 8080 Reset Signal, Active Low */ PIN 3 = pDBIN ; /* 8080 Data bus In Signal, Active High */ PIN 4 = na1 ; /* */ PIN 5 = JMPA15 ; /* */ PIN 6 = JMPA14 ; /* */ PIN 7 = JMPA13 ; /* */ PIN 8 = JMPA12 ; /* */ PIN 9 = JMPA11 ; /* */ PIN 10 = JMPA10 ; /* */ PIN 11 = JMPA9 ; /* */ PIN 13 = JMPA8 ; /* */

/*** OUTPUT PINS ********************* DESCRIPTION

****************************/ PIN 14 = CCDSB ; /* Command/Control Disable, Active Low */ PIN 15 = na2 ; /* CCDSB prevents memory from responding */ PIN 16 = DI0 ; /* */ PIN 17 = DI1 ; /* */ PIN 18 = DI2 ; /* */ PIN 19 = DI3 ; /* */ PIN 20 = DI4 ; /* */ PIN 21 = DI5 ; /* */ PIN 22 = DI6 ; /* */ PIN 23 = DI7 ; /* */

/****** PIN NODES ******************** DESCRIPTION

****************************/ PINNODE 25 = Q0 ; /* */ PINNODE 26 = Q1 ; /* */ PINNODE 27 = Q2 ; /* */ PINNODE 28 = na3 ; /* */ PINNODE 29 = na4 ; /* */ PINNODE 30 = na5 ; /* */ PINNODE 31 = na6 ; /* */ PINNODE 32 = na7 ; /* */ PINNODE 33 = na8 ; /* */ PINNODE 34 = na9 ; /* */

field jmpadr = [JMPA15,JMPA14,JMPA13,JMPA12,JMPA11,JMPA10,JMPA9,JMPA8]; field data = [DI7,DI6,DI5,DI4,DI3,DI2,DI1,DI0]; field count = [Q2, Q1, Q0];

$define S0 'b'000 $define S1 'b'001 $define S2 'b'010 $define S3 'b'011 $define S4 'b'100 $define S5 'b'101 $define S6 'b'110 $define S7 'b'111

!CCDSB = Q2 # Q1; /* Disable Command/Control outputs if count is > 1

*/ data.oe = !CCDSB & pDBIN; /* Enable data bus if count is > 1 and the data bus is IN */

data = 'h'C3 & count:S3 # 'h'00 & count:S5 # jmpadr & count:S7;

count.ck = CLK16M; count.sp = 'b'000;

SEQUENCE count { /* If count='d'0 - data.oe='b'0 CCDSB='b'1 */ PRESENT S0 if !pRESET next S1; /* If pRESET is low, continue */ if pRESET next S0; /* If pRESET is high, loop */

/* Wait for reset to go high */ PRESENT S1 if pRESET next S2; /* If pRESET is high, continue */ if !pRESET next S1;

/* If count > 'd'1 then data.oe='b'1,CCDSB='b'0 */

/* Wait for pDBIN to go high */ PRESENT S2 if pDBIN next S3; /* If pDBIN is high, continue */ if !pRESET next S0; if !pDBIN next S2;

/* If count=S3 data='h'C3 */ PRESENT S3 if !pDBIN next S4; /* If pDBIN is low, continue */ if !pRESET next S0; if pDBIN next S3;

PRESENT S4 if pDBIN next S5; /* If pDBIN is high, continue */ if !pRESET next S0; if !pDBIN next S4;

/* If count=S5 data='h'00 */ PRESENT S5 if !pDBIN next S6; /* If pDBIN is low, continue */ if !pRESET next S0; if pDBIN next S5;

PRESENT S6 if pDBIN next S7; /* If pDBIN is high, continue */ if !pRESET next S0; if !pDBIN next S6;

/* If count=S7 data=JMPADR */ PRESENT S7 if !pDBIN next S0; /* If pDBIN is low, go to the beginning */ if !pRESET next S0; if pDBIN next S7; }

.SIM file:

Name PowerOnJump; PartNo 00; Date 8/15/2006; Revision 01; Designer Engineer; Company Stockly Electronics; Assembly None; Location ; Device v750c;

ORDER: CLK16M, pDBIN, pRESET, jmpadr, CCDSB, count, data;

VECTORS: C01 'AA' ************ C01 'AA' ************ C00 'AA' ************ C00 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C00 'AA' ************ C01 'AA' ************ C01 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************ C11 'AA' ************ C11 'AA' ************ C01 'AA' ************ C01 'AA' ************

Reply to
logjam

From here, you are on your own....

I will add that CUPL can append the Sim vectors to the JED file, so you can (on a good programmer) run a full HW vector test, after device PGM. That can be usefull, when you have a green design, and are not sure if the PCB is valid.

-jg

Reply to
Jim Granville

I think I've come up with a "better" way to do it. This one uses the data input strobe as the clock for the flip flops. Much cleaner. The only thing I can't quite figure out how to do is make the SPLD power up with sequence S3. This really isn't a BIG deal since the microprocessor has to go through a reset sequence at power-up, but its annoying to think about...

I'd like the SPLD to power up with STSDSB high and data.oe=0 (count = S3).

Grant

$define S0 'b'00 $define S1 'b'01 $define S2 'b'10 $define S3 'b'11

STSDSB = count:S3; /* Disable Status outputs if count is < S3 */

data.oe = !STSDSB; /* Enable data bus if count is < S3 */

data = 'h'C3 & count:S0 # /* First byte is the C3 jump instruction */ 'h'00 & count:S1 # /* Second is the low address location */ jmpadr & count:S2; /* Third is the high address location */

count.ck = !pDBIN; count.sp = 'b'0; count.ar = !pRESET;

SEQUENCE count { PRESENT S0 next S1; PRESENT S1 next S2; PRESENT S2 next S3; PRESENT S3 next S3; }

Reply to
logjam

I'm not going to try and decode the full state details, but here are some tips : In any state engine, the states are abitrary, so you can shuffle S0..S3 to amy mapping, if POR gives 'b'00 and you want S3 @ POR, then define S3 as 'b'00.

If you also want it to stall later at S3, then you need to add an alias state, ( brings this to 5, one of which is an entry state ), which will cost one more bit.

-jg

Reply to
Jim Granville

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